REMARC : Reconfigurable Multimedia Array Coprocessor

This paper describes a new recon gurable processor architecture called REMARC (Recon gurable Multimedia Array Coprocessor). REMARC is a recon gurable coprocessor that is tightly coupled to a main RISC processor and consists of a global control unit and 64 programmable logic blocks called nano processors. REMARC is designed to accelerate multimedia applications, such as video compression, decompression, and image processing. These applications typically use 8bit or 16-bit data therefore, each nano processor has a 16-bit datapath that is much wider than those of other recon gurable coprocessors. We have developed a programming environment for REMARC and several realistic application programs, DES encryption, MPEG-2 decoding, and MPEG-2 encoding. REMARC achieves speedups ranging from a factor of 2.3 to 21.2 on these applications.

[1]  Marc Tremblay,et al.  VIS speeds new media processing , 1996, IEEE Micro.

[2]  André DeHon,et al.  MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[3]  Ruby B. Lee.  Subword parallelism with MAX-2 , 1996, IEEE Micro.

[4]  Kunle Olukotun,et al.  A software-hardware cosynthesis approach to digital system simulation , 1994, IEEE Micro.

[5]  Jan M. Rabaey,et al.  A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths , 1992 .

[6]  Uri C. Weiser,et al.  MMX technology extension to the Intel architecture , 1996, IEEE Micro.

[7]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[8]  Konstantinos Konstantinides,et al.  Image and video compression standards , 1995 .

[9]  Michael D. Smith,et al.  Tracing with Pixie , 1991 .

[10]  Gerry Kane,et al.  MIPS RISC Architecture , 1987 .

[11]  Bernard P. Zajac.  Applied cryptography: Protocols, algorithms, and source code in C , 1994 .

[12]  Wen-Hsiung Chen,et al.  A Fast Computational Algorithm for the Discrete Cosine Transform , 1977, IEEE Trans. Commun..

[13]  Michael J. Flynn,et al.  A comparison of hardware prefetching techniques for multimedia benchmarks , 1996, Proceedings of the Third IEEE International Conference on Multimedia Computing and Systems.

[14]  Ulrich Schmidt,et al.  Wavefront array processor for video applications , 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[15]  I. Tamitani,et al.  A 1.5 W single-chip MPEG2 MP@ML encoder with low power motion estimation and clocking , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[16]  Michael D. Smith,et al.  PRISC software acceleration techniques , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[17]  J. M. Rabaey,et al.  A 2.4 GOPS data-driven reconfigurable multiprocessor IC for DSP , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[18]  Ralph Wittig,et al.  OneChip: an FPGA processor with reconfigurable logic , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.