A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA

This paper presents a novel high-resolution, high-precision time-to-digital converter (TDC) architecture targeting an FPGA implementation. The proposed architecture relies on multiple parallel tapped-delay lines, taking advantage of the fast dedicated carry-chains available within modern FPGAs. Moreover, the architecture presented in this work enables to overcome resolution limitation imposed by minimal delays, providing significant resolution enchancement over the widespread single tapped-delay line architecture. A TDC with 10 ps resolution and 24 ps precision has been implemented on a 130 nm fabrication process Virtex-II Pro FPGA. The results obtained using 10 parallel tapped-delay lines, each featuring ∼27 ps resolutions, show that over 5× resolution enchancement factors can be obtained over a single tapped delay line architecture.

[1]  Juha Kostamovaara,et al.  On-Chip Voltage Reference-Based Time-to-Digital Converter for Pulsed Time-of-Flight Laser Radar Measurements , 2009, IEEE Transactions on Instrumentation and Measurement.

[2]  J.W. Haslett,et al.  A Fine Resolution TDC Architecture for Next Generation PET Imaging , 2007, IEEE Transactions on Nuclear Science.

[3]  Jian Song,et al.  A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays , 2006, IEEE Transactions on Nuclear Science.

[4]  Guo-Ruey Tsai,et al.  FPGA-Based High Area Efficient Time-To-Digital , 2006 .

[5]  Jinyuan Wu,et al.  The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay , 2008, 2008 IEEE Nuclear Science Symposium Conference Record.

[6]  Marcin Kowalski,et al.  High-resolution time-interval measuring system implemented in single FPGA device , 2004 .

[7]  J. Kostamovaara,et al.  A CMOS time-to-digital converter with better than 10 ps single-shot precision , 2006, IEEE Journal of Solid-State Circuits.

[8]  Mounir Boukadoum,et al.  A Multihit Time-to-Digital Converter Architecture on FPGA , 2009, IEEE Transactions on Instrumentation and Measurement.

[9]  Gordon Russell,et al.  A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability , 2007, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07).

[10]  A.A. Abidi,et al.  A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue , 2008, IEEE Journal of Solid-State Circuits.

[11]  Edoardo Charbon,et al.  A 17ps time-to-digital converter implemented in 65nm FPGA technology , 2009, FPGA '09.