Comprehensive Performance Benchmarking of III-V and Si nMOSFETs (Gate Length = 13 nm) Considering Supply Voltage and OFF-Current

Comprehensive performance benchmarking results for III-V and Si nanowire nMOSFETs (gate length of 13 nm) are reported based on the atomistic full-band ballistic quantum transport simulation including the effects of parasitic resistance and capacitance. After optimizing the source/drain doping for III-V nMOSFETs (to balance source exhaustion versus tunneling leakage), the current, capacitance, and switching delay (CV/I) metrics are compared across InAs, GaAs, and Si devices with different crystal orientations at various supply voltage (VDD) and OFF-current (IOFF) targets. III-V nMOSFETs are projected to improve over Si (e.g., up to ~50% reduction in gate-loaded CV/I) for low-power operation (low VDD, low IOFF) while they lose advantage in the high-performance (high VDD, high IOFF target) region. We also provide analytical models for the effects of carrier effective mass and physically explain how the performance comparison of III-V versus Si changes with device scaling.

[1]  E.J. Nowak,et al.  The effective drive current in CMOS inverters , 2002, Digest. International Electron Devices Meeting,.

[2]  Ian A. Young,et al.  Source/Drain Doping Effects and Performance Analysis of Ballistic III-V n-MOSFETs , 2015, IEEE Journal of the Electron Devices Society.

[3]  Mark S. Lundstrom,et al.  Nanoscale Transistors: Device Physics, Modeling and Simulation , 2005 .

[4]  S. Datta.  Quantum Transport: Atom to Transistor , 2004 .

[5]  Mark S. Lundstrom,et al.  Engineering Nanowire n-MOSFETs at $L_{g}<8~{\rm nm}$ , 2013, IEEE Transactions on Electron Devices.

[6]  T. Boykin,et al.  III–V FET channel designs for high current densities and thin inversion layers , 2010, 68th Device Research Conference.

[7]  L. Selmi,et al.  Performance Benchmarking and Effective Channel Length for Nanoscale InAs, ${\rm In}_{0.53}{\rm Ga}_{0.47}{\rm As}$ , and sSi n-MOSFETs , 2014, IEEE Transactions on Electron Devices.

[8]  Jeffrey Bokor,et al.  Ultimate device scaling: Intrinsic performance comparisons of carbon-based, InGaAs, and Si field-effect transistors for 5 nm gate length , 2011, 2011 International Electron Devices Meeting.

[9]  T. Boykin,et al.  Diagonal parameter shifts due to nearest-neighbor displacements in empirical tight-binding theory , 2002 .

[10]  Yang Liu,et al.  Performance Comparisons of III–V and Strained-Si in Planar FETs and Nonplanar FinFETs at Ultrashort Gate Length (12 nm) , 2012, IEEE Transactions on Electron Devices.

[11]  R. Kotlyar,et al.  Effects of Surface Orientation on the Performance of Idealized III–V Thin-Body Ballistic n-MOSFETs , 2011, IEEE Electron Device Letters.

[12]  R. Chau,et al.  Logic performance evaluation and transport physics of Schottky-gate III–V compound semiconductor quantum well field effect transistors for power supply voltages (VCC) ranging from 0.5v to 1.0v , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[13]  Characteristic Features of 1-D Ballistic Transport in Nanowire MOSFETs , 2008, IEEE Transactions on Nanotechnology.

[14]  Gerhard Klimeck,et al.  Valence band effective-mass expressions in the sp 3 d 5 s * empirical tight-binding model applied to a Si and Ge parametrization , 2004 .

[15]  S. Laux,et al.  The ballistic FET: design, capacitance and speed limit , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[16]  Mark S. Lundstrom,et al.  Theory of ballistic nanotransistors , 2003 .

[17]  M. Luisier,et al.  OMEN an Atomistic and Full-Band Quantum Transport Simulator for post-CMOS Nanodevices , 2008, 2008 8th IEEE Conference on Nanotechnology.

[18]  A. Gnudi,et al.  Band-Structure Effects in Ultrascaled Silicon Nanowires , 2007, IEEE Transactions on Electron Devices.

[19]  Dmitri E. Nikonov,et al.  Energy efficiency comparison of nanowire heterojunction TFET and Si MOSFET at Lg=13nm, including P-TFET and variation considerations , 2013, 2013 IEEE International Electron Devices Meeting.

[20]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[21]  Lizzit Daniel,et al.  Performance Benchmarking and Effective Channel Length for Nanoscale InAs, In0.53Ga0.47As, and sSi n-MOSFETs , 2014 .