A Multi-line Arbiter PUF with Improved Reliability and Uniqueness

Physically Unclonable Function (PUF) with non-clonability is mainly studied in two application scenarios of authentication and key generation. As a kind of strong PUF design, APUF (Arbiter-Based Physically Unclonable Function) and its variants have gained wide attention. However, low uniqueness and vulnerability to external environment changes are known as two major problems of APUF implemented on FPGAs. In this paper, we design a multi-line APUF structure with selection function, which based on the proportional relation between reliability and signal delay difference, to improve the reliability. We also replicate multiple same selector pairs of APUF to improve the uniqueness of APUF by reducing bias from ambient noise. From the experimental results on Xilinx Virtex-5 FPGA boards, we show that the uniqueness and steadiness of the responses from our multi-line APUF design is approximately ideal value, which is better than original APUF and DAPUF. It also indicates that this APUF design has high stabilization rate under 0°C to 50°C.

[1]  Mitsugu Iwamoto,et al.  Q-Class Authentication System for Double Arbiter PUF , 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[2]  Srinivas Devadas,et al.  Silicon physical random functions , 2002, CCS '02.

[3]  Róbert Lórencz,et al.  Proposal and Properties of Ring Oscillator-Based PUF on FPGA , 2016, J. Circuits Syst. Comput..

[4]  Srinivas Devadas,et al.  FPGA PUF using programmable delay lines , 2010, 2010 IEEE International Workshop on Information Forensics and Security.

[5]  Daniel E. Holcomb,et al.  Using Statistical Models to Improve the Reliability of Delay-Based PUFs , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[6]  Helena Handschuh,et al.  Hardware Intrinsic Security from Physically Unclonable Functions , 2010, Towards Hardware-Intrinsic Security.

[7]  Kris Gaj,et al.  Implementation of efficient SR-Latch PUF on FPGA and SoC devices , 2017, Microprocess. Microsystems.

[8]  Jorge Guajardo,et al.  FPGA Intrinsic PUFs and Their Use for IP Protection , 2007, CHES.

[9]  Helper Data,et al.  Reliable and efficient PUF-based key generation using pattern matching , 2011 .

[10]  Patrick Schaumont,et al.  A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions , 2011, IACR Cryptol. ePrint Arch..

[11]  Daisuke Suzuki,et al.  The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes , 2010, CHES.

[12]  Katashita Toshihiro,et al.  Performance Evaluation of Physical Unclonable FUnctions on Kintex-7 FPGA , 2013 .

[13]  Chip-Hong Chang,et al.  FPGA implementation of modeling attack resistant arbiter PUF with enhanced reliability , 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

[14]  Jorge Guajardo,et al.  Extended abstract: The butterfly PUF protecting IP on every FPGA , 2008, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust.

[15]  Xuelong Zhang,et al.  Highly stable data SRAM-PUF in 65nm CMOS process , 2013, 2013 IEEE 10th International Conference on ASIC.

[16]  Srinivas Devadas,et al.  Identification and authentication of integrated circuits , 2004, Concurr. Pract. Exp..

[17]  G. Edward Suh,et al.  Physical Unclonable Functions for Device Authentication and Secret Key Generation , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[18]  Kazukuni Kobara,et al.  Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays , 2014, J. Inf. Process..

[19]  Mitsugu Iwamoto,et al.  A New Arbiter PUF for Enhancing Unpredictability on FPGA , 2015, TheScientificWorldJournal.

[20]  Mitsugu Iwamoto,et al.  A new mode of operation for arbiter PUF to improve uniqueness on FPGA , 2014, 2014 Federated Conference on Computer Science and Information Systems.

[21]  Bin Chen,et al.  A Robust SRAM-PUF Key Generation Scheme Based on Polar Codes , 2017, GLOBECOM 2017 - 2017 IEEE Global Communications Conference.

[22]  Srinivas Devadas,et al.  Controlled physical random functions , 2002 .

[23]  Srinivas Devadas,et al.  Controlled physical random functions , 2002, 18th Annual Computer Security Applications Conference, 2002. Proceedings..

[24]  Marten van Dijk,et al.  A technique to build a secret key in integrated circuits for identification and authentication applications , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).