Logic optimization of AES S-Box

This paper presents the implementation of Rijndael S-Box using combinational logic for the SubByte transformation in the Advanced Encryption Standard algorithm for ASIC. The main focus of this project is on achieving reduction in area occupancy and power consumption for the S-box module. We have realized an optimized implementation of the S-box in the Verilog HDL, and have subsequently synthesized it using 90nm CMOS standard cell library. Using a novel method of design reuse in the S-Box logic, the optimized design implemented, consumes 146 cells and the total power dissipation of 32,911 nW which is significantly lower when compared to the existing digital logic implementations.

[1]  C. Senthilpari,et al.  A low power hardware implementation of S-Box for Advanced Encryption Standard , 2014, 2014 11th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON).

[2]  P.V.S. Shastry,et al.  A combinational logic implementation of S-box of AES , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

[3]  Saurabh Kumar,et al.  Low latency VLSI architecture of S-box for AES encryption , 2013, 2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT).

[4]  Ye Li,et al.  A low-power and cost-effective AES chip design for healthcare devices , 2012, Proceedings of 2012 IEEE-EMBS International Conference on Biomedical and Health Informatics.

[5]  Ingrid Verbauwhede,et al.  Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm , 2001, CHES.

[6]  Cheng Wang,et al.  Using a pipelined S-box in compact AES hardware implementations , 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

[7]  Samir Palnitkar,et al.  Verilog HDL: a guide to digital design and synthesis , 1996 .

[8]  Warsuzarina Mat Jubadi,et al.  Design of AES S-box using combinational logic optimization , 2010, 2010 IEEE Symposium on Industrial Electronics and Applications (ISIEA).

[9]  Bahram Rashidi,et al.  Implementation of An Optimized and Pipelined Combinational Logic Rijndael S-Box on FPGA , 2013 .

[10]  P. S. Abhijith,et al.  High performance hardware implementation of AES using minimal resources , 2013, 2013 International Conference on Intelligent Systems and Signal Processing (ISSP).

[11]  R. Borhan,et al.  Successful implementation of AES algorithm in hardware , 2012, 2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA).

[12]  Poonam Kadam,et al.  Pipelined Implementation of Dynamic Rijndael S-Box , 2015 .

[13]  William Stallings,et al.  Cryptography and network security , 1998 .