Cycle elimination method to construct VLSI oriented LDPC codes

Recently VLSI implementation oriented LDPC codes have been invented and drawn more and more attention. The main feature of the type of code is that its H matrix is made of a set of square permutation L×L matrices. Each permutation matrix is an identity matrix whose rows have been cyclically shifted by a set of amount. This paper presents a cycle elimination algorithm to improve the girth performance of such codes. In particular, the new approach tries to find all the short cycles existing in the base matrix and eliminate them through setting the cyclically shifted values of the square permutation matrixes. The efficiency of the cycle elimination algorithm is verified through constructing a set of different rate LDPC irregular/regular codes. Simulation and hardware measurement results show that the error floor of cycle elimination constructed codes is suppressed to a much lower level without other performance penalty. For example, the irregular rate 1/2 code achieves a block error rate of 10 at SNR 1.9 dB without presence of error floor.