Handling the complexity of routing problem in modern VLSI design

In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pins and ports of circuit gates and blocks. Traditionally, VLSI routing is an important design step in the sense that the quality of routing solution has great impact on various design metrics such circuit timing, power consumption, chip reliability and manufacturability etc. As the advancing VLSI design enters the nanometer era, the routing success (routability issue) has been arising as one of the most critical problems in back-end design. In one aspect, the degree of design complexity is increasing dramatically as more and more modules are integrated onto the chip. Much higher chip density leads to higher routing demands and potentially more risks in routing failure. In another aspect, with decreasing design feature size, there are more complex design rules imposed to ensure manufacturability. These design rules are hard to satisfy and they usually create more barriers for achieving routing closure (i.e., generate DRC free routing solution) and thus affect chip time to market (TTM) plan. In general, the behavior and performance of routing are affected by three consecutive phases: placement phase, global routing phase and detailed routing phase in a typical VLSI physical design flow. Traditional CAD tools handle each of the three phases independently and the global picture of the routability issue is neglected. Different from conventional approaches which propose tools and algorithms for one particular design phase, this thesis investigates the routability issue from all three phases and proposes a series of systematic solutions to build a more generic flow and improve quality of results (QoR). For the placement phase, we will introduce a mixed-sized placement refinement tool for alleviating congestion after placement. The tool shifts and relocates modules based on a global routing estimation. For the global routing phase, a very fast and effective global router is

[1]  Chris C. N. Chu FLUTE: fast lookup table based wirelength estimation technique , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[2]  Jarrod A. Roy,et al.  Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Majid Sarrafzadeh,et al.  Predictable routing , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[4]  Ulrich Brenner,et al.  An effective congestion driven placement framework , 2002, ISPD '02.

[5]  Majid Sarrafzadeh,et al.  Routability driven white space allocation for fixed-die standard-cell placement , 2002, ISPD '02.

[6]  Martin D. F. Wong,et al.  Archer: a history-driven global routing algorithm , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[7]  Muhammet Mustafa Ozdal Detailed-Routing Algorithms for Dense Pin Clusters in Integrated Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Yue Xu,et al.  FastRoute 4.0: Global router with efficient via minimization , 2009, 2009 Asia and South Pacific Design Automation Conference.

[9]  Ting-Chi Wang,et al.  NTHU-Route 2.0: A fast and stable global router , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[10]  Jarrod A. Roy,et al.  High-Performance Routing at the Nanometer Scale , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Yanheng Zhang,et al.  RegularRoute: an efficient detailed router with regular routing patterns , 2011, ISPD '11.

[12]  Yao-Wen Chang,et al.  NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Jason Cong,et al.  Routability-driven placement and white space allocation , 2004, ICCAD 2004.

[14]  Feng Zhou,et al.  Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction , 2002, SLIP '02.

[15]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[16]  Yue Xu,et al.  An auction based pre-processing technique to determine detour in global routing , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[17]  Carl Ebeling,et al.  PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[18]  Alberto L. Sangiovanni-Vincentelli,et al.  A Detailed Router Based on Incremental Routing Modifications: Mighty , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Rob A. Rutenbar,et al.  A new FPGA detailed routing approach via search-based Booleansatisfiability , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Takeshi Yoshimura,et al.  Efficient Algorithms for Channel Routing , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Danny Rittman,et al.  Nanometer DFM – The tip of the ice , 2008 .

[22]  Yao-Wen Chang,et al.  Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[23]  Joseph R. Shinnerl,et al.  mPL6: a robust multilevel mixed-size placement engine , 2005, ISPD '05.

[24]  Chris C. N. Chu,et al.  An efficient and effective detailed placement algorithm , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[25]  Peter Spindler,et al.  Fast and accurate routing demand estimation for efficient routability-driven placement , 2007 .

[26]  Hai Zhou,et al.  Track assignment: a desirable intermediate step between global routing and detailed routing , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[27]  Chris C. N. Chu,et al.  IPR: An Integrated Placement and Routing Algorithm , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[28]  J.A. Roy,et al.  High-performance routing at the nanometer scale , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[29]  Jarrod A. Roy,et al.  Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[30]  Majid Sarrafzadeh,et al.  Pattern routing: use and theory for increasing predictability andavoiding coupling , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  Raia Hadsell,et al.  Improved global routing through congestion estimation , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[32]  David Z. Pan,et al.  BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[33]  Jason Cong,et al.  Routability-driven placement and white space allocation , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[34]  Kun Yuan,et al.  BoxRouter 2.0: architecture and implementation of a hybrid and robust global router , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[35]  A. Hashimoto,et al.  Wire routing by optimizing channel assignment within large apertures , 1971, DAC '71.

[36]  Ting-Chi Wang,et al.  A new global router for modern designs , 2008, 2008 Asia and South Pacific Design Automation Conference.

[37]  Jason Cong,et al.  DUNE-a multilayer gridless routing system , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[38]  Yao-Wen Chang,et al.  MR: a new framework for multilevel full-chip routing , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[39]  Min Pan,et al.  FastRoute: A Step to Integrate Global Routing into Placement , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[40]  Cheng-Kok Koh,et al.  Guiding global placement with wire density , 2008, ICCAD 2008.

[41]  Chris C. N. Chu,et al.  FastPlace: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[42]  Yue Xu,et al.  FastRoute3.0: A fast and high quality global router based on virtual capacity , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[43]  Cheng-Kok Koh,et al.  Guiding global placement with wire density , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[44]  Chris C. N. Chu,et al.  FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control , 2007, 2007 Asia and South Pacific Design Automation Conference.

[45]  Michael D. Moffitt MaizeRouter: Engineering an Effective Global Router , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[46]  Chris C. N. Chu,et al.  FastRoute 2.0: A High-quality and Efficient Global Router , 2007, 2007 Asia and South Pacific Design Automation Conference.