Dual-Material Double-Gate SOI n-MOSFET: Gate Misalignment Analysis

The dual-material double-gate (DMDG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is the leading contender for sub-100-nm devices because it utilizes the benefits of both double-gate and dual-material-gate structures. One major issue of concern in the DMDG-MOSFET is the alignment between the top and the bottom gate that critically influences the device performance. In this paper, we have investigated the effects of gate misalignment in the DMDG SOI n-MOSFET. In this regard, analytical modeling and extensive simulations have been carried out to analyze the gate misalignment effects on device performance like surface potential, electric field, threshold voltage, subthreshold slope, drain-induced barrier lowering, drain current, and transconductance. Considering the fact that gate misalignment can occur on any side of the gate, both source- and drain-side misalignments have been discussed. Analytical and simulated results are found to be in good agreement, which authenticate our proposed model for the DMDG structure.

[1]  M. V. Fischetti,et al.  Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go? , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[2]  K. F. Lee,et al.  Scaling the Si MOSFET: from bulk to SOI to bulk , 1992 .

[3]  Y. Tosaka,et al.  Scaling theory for double-gate SOI MOSFET's , 1993 .

[4]  T. Sugii,et al.  Ultrafast operation of V/sub th/-adjusted p/sup +/-n/sup +/ double-gate SOI MOSFET's , 1994, IEEE Electron Device Letters.

[5]  C. Hu,et al.  A comparative study of advanced MOSFET concepts , 1996 .

[6]  Jin-Hau Kuo,et al.  Deep submicrometer double-gate fully-depleted SOI PMOS devices: a concise short-channel effect threshold voltage model using a quasi-2D approach , 1996 .

[7]  Xing Zhou,et al.  A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology , 1998 .

[8]  Ping Keung Ko,et al.  Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors , 1998 .

[9]  Ken K. Chin,et al.  Dual-material gate (DMG) field effect transistor , 1999 .

[10]  Qiang Chen,et al.  A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs , 2002 .

[11]  Mansun Chan,et al.  The gate misalignment effects of the sub-threshold characteristics of sub-100 nm DG-MOSFETs , 2002, Proceedings 2002 IEEE Hong Kong Electron Devices Meeting (Cat. No.02TH8616).

[12]  U. Langmann,et al.  Planar and vertical double gate concepts , 2002 .

[13]  Zhibin Xiong,et al.  Implementation and characterization of the double-gate MOSFET using lateral solid-phase epitaxy , 2003 .

[14]  T. Ouisse,et al.  Ultimately thin double-gate SOI MOSFETs , 2003 .

[15]  P.C.H. Chan,et al.  Fabrication of raised S/D gate-all-around transistor and gate misalignment analysis , 2003, IEEE Electron Device Letters.

[16]  Hiromi Yamauchi,et al.  Systematic electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs fabricated by a wet process , 2003 .

[17]  G. A. Armstrong,et al.  Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers , 2004, Microelectron. J..

[18]  M. J. Kumar,et al.  Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review , 2004, IEEE Transactions on Device and Materials Reliability.

[19]  M.J. Kumar,et al.  Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs , 2004, IEEE Transactions on Electron Devices.

[20]  Xinnan Lin,et al.  Characterization of double gate MOSFETs fabricated by a simple method on a recrystallized silicon film , 2004 .

[21]  M.J. Kumar,et al.  A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation , 2005, IEEE Transactions on Nanotechnology.

[22]  P.C.H. Chan,et al.  Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs , 2005, IEEE Transactions on Electron Devices.

[23]  M. Jagadesh Kumar,et al.  Diminished Short Channel Effects in Nanoscale Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect-Transistors due to Induced Back-Gate Step Potential , 2005 .

[24]  M. Vinet,et al.  Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance , 2005, IEEE Transactions on Electron Devices.

[25]  Denis Flandre,et al.  Planar double-gate SOI MOS devices: Fabrication by wafer bonding over pre-patterned cavities and electrical characterization , 2007 .

[26]  D. Querlioz,et al.  On the Ability of the Particle Monte Carlo Technique to Include Quantum Effects in Nano-MOSFET Simulation , 2007, IEEE Transactions on Electron Devices.

[27]  Te-Kuang Chiang,et al.  A New Two-Dimensional Analytical Model for Short-Channel Symmetrical Dual-Material Double-Gate Metal–Oxide–Semiconductor Field Effect Transistors , 2007 .

[28]  Mridula Gupta,et al.  Graded channel architecture : the solution for misaligned DG FD SOI n-MOSFETs , 2008 .

[29]  Chun-Chien Tsai,et al.  High-performance top and bottom double-gate low-temperature poly-silicon thin film transistors fabricated by excimer laser crystallization , 2008 .

[30]  James B. Kuo,et al.  A Compact Threshold Voltage Model for Gate Misalignment Effect of DG FD SOI nMOS Devices Considering Fringing Electric Field Effects , 2009 .