Test pattern generation for width compression in BIST

The main objectives of built-in self test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test vectors and utilize the minimum circuit area. This paper targets the problem of generating test patterns for stuck-at faults that induce compatibility relations between the primary inputs of the circuit under test. These compatibility relations can be used for designing counter-based test generator circuits with a reduced number of bits, thus requiring smaller testing time and smaller area. The proposed solution is based on an integer linear programming (ILP) formulation that builds on existing propositional satisfiability (SAT) models for test pattern generation. An ATPG tool for minimum test pattern generation for width compression (MTP-C) is described, which illustrates the practical applicability of our approach for a wide range of benchmark circuits.

[1]  Hans-Joachim Wunderlich.  Multiple distributions for biased random test patterns , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[3]  Benoit Nadeau-Dostie,et al.  A new procedure for weighted random built-in self-test , 1990, Proceedings. International Test Conference 1990.

[4]  Vishwani D. Agrawal,et al.  A transitive closure algorithm for test generation , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Paulo F. Flores,et al.  An exact solution to the minimum size test pattern problem , 2001, TODE.

[6]  S. Hellebrand,et al.  An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[7]  Tracy Larrabee,et al.  Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[9]  Nur A. Touba,et al.  Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[10]  Irith Pomeranz,et al.  A learning-based method to match a test pattern generator to a circuit-under-test , 1993, Proceedings of IEEE International Test Conference - (ITC).

[11]  Sarita Thakar,et al.  On the generation of test patterns for combinational circuits , 1993 .

[12]  Gamille Cambon,et al.  LFSR based Deterministic and Pseudo-Random Test Pattern Generator Structures , 1991 .

[13]  Paulo F. Flores,et al.  An exact solution to the minimum size test pattern problem , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[14]  Sandeep K. Gupta,et al.  A methodology to design efficient BIST test pattern generators , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[15]  Jian Liu,et al.  Test width compression for built-in self testing , 1997, Proceedings International Test Conference 1997.

[16]  Hans-Joachim Wunderlich,et al.  Pattern generation for a deterministic BIST scheme , 1995, ICCAD.

[17]  Joao Marques-Silva,et al.  Robust search algorithms for test pattern generation , 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.

[18]  S. Hellebrand,et al.  Pattern generation for a deterministic BIST scheme , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[19]  Vasco M. Manquinho,et al.  Prime implicant computation using satisfiability algorithms , 1997, Proceedings Ninth IEEE International Conference on Tools with Artificial Intelligence.

[20]  Krishnendu Chakrabarty,et al.  Design of built-in test generator circuits using width compression , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Robert K. Brayton,et al.  Combinational test generation using satisfiability , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..