Fidelity metrics for estimation models

Estimation models play a vital role in many aspects of day to day life. Extremely complex estimation models are employed in the design space exploration of SoCs, and the efficacy of these estimation models is usually measured by the absolute error of the models compared to known actual results. Such absolute error based metrics can often result in over-designed estimation models, with a number of researchers suggesting that fidelity of an estimation model (correlation between the ordering of the estimated points and the ordering of the actual points) should be examined instead of, or in addition to, the absolute error. In this paper, for the first time, we propose four metrics to measure the fidelity of an estimation model, in particular for use in design space exploration. The first two are based on two well known rank correlation coefficients. The other two are weighted versions of the first two metrics, to give importance to points nearer the Pareto front. The proposed fidelity metrics range from −1 to 1, where a value of 1 reflects a perfect positive correlation while a value of −1 reflects a perfect negative correlation. The proposed fidelity metrics were calculated for a single processor estimation model and a multiprocessor estimation model to observe their behavior, and were compared against the models' absolute error. For the multiprocessor estimation model, even though the worst average and maximum absolute error of 6.40% and 16.61% respectively can be considered reasonable in design automation, the worst fidelity of 0.753 suggests that the multiprocessor estimation model may not be as good a model (compared to an estimation model with same or higher absolute errors but a fidelity of 0.95) as depicted by its absolute accuracy, leading to an over-designed estimation model.

[1]  W. Kruskal Ordinal Measures of Association , 1958 .

[2]  Jarek Gryz,et al.  Algorithms and analyses for maximal vector computation , 2007, The VLDB Journal.

[3]  Ben Carterette,et al.  On rank correlation and the distance between rankings , 2009, SIGIR.

[4]  C. Spearman The proof and measurement of association between two things. , 2015, International journal of epidemiology.

[5]  Soheil Ghiasi,et al.  System-Level Performance Estimation for Application-Specific MPSoC Interconnect Synthesis , 2008, 2008 Symposium on Application Specific Processors.

[6]  Jeffry T. Russell,et al.  Architecture-level performance evaluation of component-based embedded systems , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[7]  Yao-Wen Chang,et al.  Performance optimization by wire and buffer sizing under the transmission line model , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[8]  J. M. Bevan,et al.  Rank Correlation Methods , 1949 .

[9]  R. Forthofer,et al.  Rank Correlation Methods , 1981 .

[10]  David Z. Pan,et al.  Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[11]  Stijn Eyerman,et al.  Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[12]  Jiang Chau Wang,et al.  A System-level Performance Evaluation Methodology for Netwrok Processors Based on Network Calculus Analytical Modeling , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[13]  Stephen E. Robertson,et al.  A new rank correlation coefficient for information retrieval , 2008, SIGIR '08.

[14]  Lieven Eeckhout,et al.  Evaluating the efficacy of statistical simulation for design space exploration , 2006, 2006 IEEE International Symposium on Performance Analysis of Systems and Software.

[15]  R. Nelsen,et al.  On the relationship between Spearman's rho and Kendall's tau for pairs of continuous random variables , 2007 .

[16]  Sri Parameswaran,et al.  Rapid runtime estimation methods for pipelined MPSoCs , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[17]  Matthias Gries,et al.  Methods for evaluating and covering the design space during early design development , 2004, Integr..