Grid-based temporal logic inference

This paper introduces a new algorithm to infer temporal logic properties of a system from data consisting of a set of finite time system traces. We propose an algorithm that generates a Signal Temporal Logic formula by discretizing the entire domain and codomain of the system traces. Unlike many popular inference algorithms which require labeled data that represents whether a trace exhibits a desired behavior (positive) or not (negative), this approach only requires positive traces to infer temporal logic properties. We present two case studies to illustrate the efficiency and accuracy of the proposed algorithm. The first is a biological network consisting of a genetic logic circuit in a bacterial cell. The second is a fault detection problem in automotive powertrain systems. We also compare the performance of the algorithm with an existing inference algorithm.

[1]  Thomas F. Knight,et al.  Idempotent Vector Design for Standard Assembly of Biobricks , 2003 .

[2]  Christel Baier,et al.  Principles of model checking , 2008 .

[3]  Dejan Nickovic,et al.  Monitoring Temporal Properties of Continuous Signals , 2004, FORMATS/FTRTFT.

[4]  Calin Belta,et al.  A Decision Tree Approach to Data Classification using Signal Temporal Logic , 2016, HSCC.

[5]  Georgios E. Fainekos,et al.  Mining parametric temporal logic properties in model-based design for cyber-physical systems , 2015, International Journal on Software Tools for Technology Transfer.

[6]  Calin Belta,et al.  Anomaly detection in cyber-physical systems: A formal methods approach , 2014, 53rd IEEE Conference on Decision and Control.

[7]  Ezio Bartocci,et al.  Data-Driven Statistical Learning of Temporal Logic Properties , 2014, FORMATS.

[8]  VARUN CHANDOLA,et al.  Anomaly detection: A survey , 2009, CSUR.

[9]  Calin Belta,et al.  Temporal logic inference for classification and prediction from data , 2014, HSCC.

[10]  Ernst Weber,et al.  A Modular Cloning System for Standardized Assembly of Multigene Constructs , 2011, PloS one.

[11]  Oded Maler,et al.  Robust Satisfaction of Temporal Logic over Real-Valued Signals , 2010, FORMATS.

[12]  Jacob Beal,et al.  Synthetic Biology Open Language Visual (SBOL Visual) Version 2.0 , 2018, J. Integr. Bioinform..

[13]  Sanjit A. Seshia,et al.  Mining Requirements From Closed-Loop Control Models , 2015, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..