Multiprocessor System-on-Chip - Hardware Design and Tool Integration

Part 1: Application Mapping and Communication Infrastructure: Virtualization in NOCs--Enhanced MPSOC Robustness and Performance Verification.-HW Support to Exploit Parallelism in Homogeneous and Heterogeneous Multicore System-on-Chip.-PALLAS: Mapping Applications onto Manycore.-Part 2: Reconfigurable Hardware in Multiprocessor Systems: Adaptive Multiprocessor System on Chip Architecture.-Designing FPGA Systems with Many Processors.-Part 3: Physical Design of Multiprocessor Systems: Design tools and methods for chip physical design.-Challenges in Physical Design for Multi- and Manycore Hardware Architectures.

[1]  Chih-Jen Lin,et al.  LIBSVM: A library for support vector machines , 2011, TIST.

[2]  Timothy Mark Pinkston,et al.  On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[3]  Chris R. Jesshope,et al.  Evaluating CMPs and Their Memory Architecture , 2009, ARCS.

[4]  Kunle Olukotun,et al.  Niagara: a 32-way multithreaded Sparc processor , 2005, IEEE Micro.

[5]  Kurt Keutzer,et al.  Parallel computing with patterns and frameworks , 2010, XRDS.

[6]  John Cocke,et al.  Programming languages and their compilers: Preliminary notes , 1969 .

[7]  Yuval Rabani,et al.  Local divergence of Markov chains and the analysis of iterative load-balancing schemes , 1998, Proceedings 39th Annual Symposium on Foundations of Computer Science (Cat. No.98CB36280).

[8]  M. Meitinger,et al.  FlexPath NP - A network processor architecture with flexible processing paths , 2008, 2008 International Symposium on System-on-Chip.

[9]  Jitendra Malik,et al.  Large Displacement Optical Flow: Descriptor Matching in Variational Motion Estimation , 2011, IEEE Transactions on Pattern Analysis and Machine Intelligence.

[10]  Michael Paterakis,et al.  Energy-conserving access protocols for transmitting data in unicast and broadcast mode , 2000, 11th IEEE International Symposium on Personal Indoor and Mobile Radio Communications. PIMRC 2000. Proceedings (Cat. No.00TH8525).

[11]  Wolfgang Fichtner,et al.  Practical design of globally-asynchronous locally-synchronous systems , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[12]  Li-Shiuan Peh,et al.  Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks , 2007, IEEE Transactions on Parallel and Distributed Systems.

[13]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[14]  Fred J. Pollack New microarchitecture challenges in the coming generations of CMOS process technologies (keynote address)(abstract only) , 1999, MICRO.

[15]  Simone Orcioni,et al.  Power analysis methodology and library in SystemC , 2005, SPIE Microtechnologies.

[16]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[17]  Stephen P. Boyd,et al.  Temperature-aware processor frequency assignment for MPSoCs using convex optimization , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[18]  Lizy Kurian John,et al.  Scaling to the end of silicon with EDGE architectures , 2004, Computer.

[19]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[20]  John Kubiatowicz,et al.  Exploiting prediction to reduce power on buses , 2004, 10th International Symposium on High Performance Computer Architecture (HPCA'04).

[21]  Marcelo de Oliveira Johann,et al.  Channel based routing in channel-less circuits , 2006, ISCAS.

[22]  Andrew S. Tanenbaum,et al.  Computer Networks , 1981 .

[23]  Ahmed Amine Jerraya,et al.  Multiprocessor System-on-Chip (MPSoC) Technology , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  Todor Stefanov,et al.  pn: A Tool for Improved Derivation of Process Networks , 2007, EURASIP J. Embed. Syst..

[25]  Paul E. Landman,et al.  Low-power architectural design methodologies , 1995 .

[26]  Mircea R. Stan,et al.  Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[27]  Kees Goossens,et al.  Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications , 2010, DSD 2010.

[28]  Thomas Brox,et al.  High Accuracy Optical Flow Estimation Based on a Theory for Warping , 2004, ECCV.

[29]  Richard Szeliski,et al.  A Database and Evaluation Methodology for Optical Flow , 2007, 2007 IEEE 11th International Conference on Computer Vision.

[30]  P.T. Wolkotte,et al.  Energy Model of Networks-on-Chip and a Bus , 2005, 2005 International Symposium on System-on-Chip.

[31]  Qinru Qiu,et al.  Partitioned bus coding for energy reduction , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[32]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[33]  Paul Feautrier,et al.  Automatic Parallelization in the Polytope Model , 1996, The Data Parallel Programming Model.

[34]  Jörg Henkel,et al.  Avalanche: an environment for design space exploration and optimization of low-power embedded systems , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[35]  George Kornaros Temporal coding schemes for energy efficient data transmission in Systems-on-Chip , 2009, 2009 Seventh Workshop on Intelligent solutions in Embedded Systems.

[36]  Andrew T. Young,et al.  Back of the Envelope , 1980, 99 Variations on a Proof.

[37]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[38]  Onur Mutlu,et al.  Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers , 2009, IEEE Micro.

[39]  Henry Hoffmann,et al.  On-Chip Interconnection Architecture of the Tile Processor , 2007, IEEE Micro.

[40]  Fabien Clermidy,et al.  An asynchronous NOC architecture providing low latency service and its multi-level design framework , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[41]  John Shalf,et al.  SEJITS: Getting Productivity and Performance With Selective Embedded JIT Specialization , 2010 .

[42]  Kees G. W. Goossens,et al.  The aethereal network on chip after ten years: Goals, evolution, lessons, and future , 2010, Design Automation Conference.

[43]  H. Corporaal,et al.  Design-Time Application Exploration for MP-SoC Customized Run-Time Management , 2005, 2005 International Symposium on System-on-Chip.

[44]  Luca Benini,et al.  A survey of design techniques for system-level dynamic power management , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[45]  Mark Bohr,et al.  The new era of scaling in an SoC world , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[46]  Luc Moreau,et al.  Resource aware programming , 2005, TOPL.

[47]  Vivek Sarkar,et al.  X10: an object-oriented approach to non-uniform cluster computing , 2005, OOPSLA '05.

[48]  Kurt Keutzer,et al.  Acceleration of market value-at-risk estimation , 2009, WHPCF '09.

[49]  Yusuf Leblebici,et al.  Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation , 2006, 2006 IFIP International Conference on Very Large Scale Integration.

[50]  D. Geer,et al.  Chip makers turn to multicore processors , 2005, Computer.

[51]  Tadao Kasami,et al.  An Efficient Recognition and Syntax-Analysis Algorithm for Context-Free Languages , 1965 .

[52]  David Wentzlaff,et al.  Processor: A 64-Core SoC with Mesh Interconnect , 2010 .

[53]  Jan M. Rabaey,et al.  Architectural power analysis: The dual bit type method , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[54]  Reaz Hoque Corba 3 , 1998 .

[55]  Miltos D. Grammatikakis,et al.  System-Level Tools for NoC-Based Multi-Core Design , 2010 .

[56]  Nicholas Carriero,et al.  How to write parallel programs: a guide to the perplexed , 1989, CSUR.

[57]  Sharad Malik,et al.  Challenges and Solutions for Late- and Post-Silicon Design , 2008, IEEE Design & Test of Computers.

[58]  Yusuf Leblebici,et al.  Analysis and Optimization of MPSoC Reliability , 2006, J. Low Power Electron..

[59]  L. Benini,et al.  Cycle-accurate simulation of energy consumption in embedded systems , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[60]  Srinivasan Murali,et al.  SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[61]  Radu Marculescu,et al.  Energy- and performance-aware mapping for regular NoC architectures , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[62]  Yun Zhang,et al.  Revisiting the Sequential Programming Model for Multi-Core , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[63]  Mary Jane Irwin,et al.  Some issues in gray code addressing , 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

[64]  Kurt Keutzer,et al.  Fast support vector machine training and classification on graphics processors , 2008, ICML '08.

[65]  Christian Müller-Schloer,et al.  Organic computing: on the feasibility of controlled emergence , 2004, CODES+ISSS '04.

[66]  H. Peter Hofstee,et al.  Power efficient processor architecture and the cell processor , 2005, 11th International Symposium on High-Performance Computer Architecture.

[67]  Erik Yama Étienne Hyper-threading , 2012 .

[68]  D. Donoho,et al.  SPIR-iT : Autocalibrating Parallel Imaging Compressed Sensing , 2008 .

[69]  Kees G. W. Goossens,et al.  Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration , 2008, 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications.

[70]  Paolo Crippa,et al.  System-Level Power Analysis Methodology Applied to the AMBA AHB Bus , 2003, DATE.

[71]  Wolfgang Nebel,et al.  Power Management Aware Low Leakage Behavioural Synthesis , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[72]  Mache Creeger,et al.  Multicore CPUs for the Masses , 2005, QUEUE.

[73]  Wayne H. Wolf,et al.  The future of multiprocessor systems-on-chips , 2004, Proceedings. 41st Design Automation Conference, 2004..

[74]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[75]  Giovanni De Micheli,et al.  Robust system design with uncertain information , 2003, First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings..

[76]  Mary Shaw,et al.  An Introduction to Software Architecture , 1993, Advances in Software Engineering and Knowledge Engineering.

[77]  James Demmel,et al.  Communication-optimal Parallel and Sequential QR and LU Factorizations , 2008, SIAM J. Sci. Comput..

[78]  Fernando Gehm Moraes,et al.  Exploring NoC mapping strategies: an energy and timing aware technique , 2005, Design, Automation and Test in Europe.

[79]  Jan Reineke,et al.  Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[80]  Peter Cumming,et al.  The TI OMAP™ Platform Approach to SOC , 2003 .

[81]  Christopher Hughes,et al.  Scalable HMM based inference engine in large vocabulary continuous speech recognition , 2009, 2009 IEEE International Conference on Multimedia and Expo.

[82]  Eric Senn,et al.  SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications , 2005, EURASIP J. Adv. Signal Process..

[83]  Pieter van der Wolf,et al.  Real-Time Analysis for Memory Access in Media Processing SoCs: A Practical Approach , 2008, 2008 Euromicro Conference on Real-Time Systems.

[84]  Chi-Ying Tsui,et al.  Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[85]  Shufu Mao,et al.  Collaborative Monitors for Embedded System Security , 2006 .

[86]  Peter Sanders,et al.  Randomized Priority Queues for Fast Parallel Access , 1998, J. Parallel Distributed Comput..

[87]  Wonyong Sung,et al.  Parallel scalability in speech recognition , 2009, IEEE Signal Processing Magazine.

[88]  David Blaauw,et al.  A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation , 2011, IEEE Journal of Solid-State Circuits.

[89]  Kees G. W. Goossens,et al.  Aelite: A flit-synchronous Network on Chip with composable and predictable services , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[90]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[91]  Kurt Keutzer,et al.  A fully data parallel WFST-based large vocabulary continuous speech recognition on a graphics processing unit , 2009, INTERSPEECH.

[92]  Kurt Keutzer,et al.  The Concurrency Challenge , 2008, IEEE Design & Test of Computers.

[93]  Sanjay Pant,et al.  A self-tuning DVS processor using delay-error detection and correction , 2005, IEEE Journal of Solid-State Circuits.

[94]  Kees G. W. Goossens,et al.  An on-chip interconnect and protocol stack for multiple communication paradigms and programming models , 2009, CODES+ISSS '09.

[95]  Erik Brockmeyer,et al.  Data Access and Storage Management for Embedded Programmable Processors , 2002, Springer US.

[96]  Kees G. W. Goossens,et al.  Efficient Service Allocation in Hardware Using Credit-Controlled Static-Priority Arbitration , 2009, 2009 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications.

[97]  Jörg Henkel,et al.  A dictionary-based en/decoding scheme for low-power data buses , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[98]  Samuel Williams,et al.  The Landscape of Parallel Computing Research: A View from Berkeley , 2006 .

[99]  Jitendra Malik,et al.  Using contours to detect and localize junctions in natural images , 2008, 2008 IEEE Conference on Computer Vision and Pattern Recognition.

[100]  Yi Zhu,et al.  Communication latency aware low power NoC synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[101]  Kurt Keutzer,et al.  Copperhead: compiling an embedded data parallel language , 2011, PPoPP '11.

[102]  Jun Shao,et al.  A Burst Scheduling Access Reordering Mechanism , 2007, 2007 IEEE 13th International Symposium on High Performance Computer Architecture.

[103]  Uri C. Weiser,et al.  Interconnect-power dissipation in a microprocessor , 2004, SLIP '04.

[104]  G. STEPHANIDES,et al.  Energy Estimation with SystemC : A Programmer ' s Perspective , 2003 .

[105]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[106]  Uming Ko,et al.  90nm low leakage SoC design techniques for wireless applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[107]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[108]  Radu Marculescu,et al.  Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[109]  Anant Agarwal,et al.  Software Standards for the Multicore Era , 2009, IEEE Micro.

[110]  Thomas D. Burd,et al.  Design issues for Dynamic Voltage Scaling , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[111]  Soraya Ghiasi,et al.  A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[112]  Jan-Michael Frahm,et al.  Fast gain-adaptive KLT tracking on the GPU , 2008, 2008 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops.

[113]  Rolf Ernst,et al.  Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[114]  Sani R. Nassif,et al.  High Performance CMOS Variability in the 65nm Regime and Beyond , 2006, 2007 IEEE International Electron Devices Meeting.

[115]  Mahmut T. Kandemir,et al.  Influence of compiler optimizations on system power , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[116]  S. Naffziger,et al.  Power and temperature control on a 90-nm Itanium family processor , 2006, IEEE Journal of Solid-State Circuits.

[117]  Li-Shiuan Peh,et al.  Leakage power modeling and optimization in interconnection networks , 2003, ISLPED '03.

[118]  Toshinori Sato,et al.  Evaluation of architecture-level power estimation for CMOS RISC processors , 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

[119]  Kurt Keutzer,et al.  Dense Point Trajectories by GPU-Accelerated Large Displacement Optical Flow , 2010, ECCV.

[120]  Anand Raghunathan,et al.  A framework for efficient and scalable execution of domain-specific templates on GPUs , 2009, 2009 IEEE International Symposium on Parallel & Distributed Processing.

[121]  Kees G. W. Goossens,et al.  Composable Resource Sharing Based on Latency-Rate Servers , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[122]  Luca Benini,et al.  System-level power optimization: techniques and tools , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[123]  H. Corporaal,et al.  Fast Multi-Dimension Multi-Choice Knapsack Heuristic for MP-SoC Run-Time Management , 2006, 2006 International Symposium on System-on-Chip.

[124]  David F. Heidel,et al.  An Overview of the BlueGene/L Supercomputer , 2002, ACM/IEEE SC 2002 Conference (SC'02).

[125]  R. Marculescu,et al.  Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[126]  Yoshinobu Inada,et al.  Order and flexibility in the motion of fish schools. , 2002, Journal of theoretical biology.

[127]  Santanu Dutta,et al.  Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems , 2001, IEEE Des. Test Comput..

[128]  Ira Krepchin,et al.  Texas Instruments Inc. , 1963, Nature.

[129]  Andreas Herkersdorf,et al.  Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[130]  Anantha Chandrakasan,et al.  Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[131]  Majid Sarrafzadeh,et al.  Memory Segmentation to Exploit Sleep Mode Operation , 1995, 32nd Design Automation Conference.

[132]  Sandip Kundu,et al.  On process variation tolerant low cost thermal sensor design in 32nm CMOS technology , 2009, GLSVLSI '09.

[133]  Orlando Moreira,et al.  Scheduling multiple independent hard-real-time jobs on a heterogeneous multiprocessor , 2007, EMSOFT '07.

[134]  Seth J. Teller,et al.  Particle Video: Long-Range Motion Estimation Using Point Trajectories , 2006, 2006 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'06).

[135]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[136]  Olivier Temam,et al.  CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[137]  Corinna Cortes,et al.  Support-Vector Networks , 1995, Machine Learning.

[138]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[139]  Lukas Kencl,et al.  Sequence-preserving adaptive load balancers , 2006, 2006 Symposium on Architecture For Networking And Communications Systems.

[140]  K. Keutzer,et al.  Our Pattern Language ( OPL ) : A Design Pattern Language for Engineering ( Parallel ) Software , 2009 .

[141]  Kurt Keutzer,et al.  Efficient, high-quality image contour detection , 2009, 2009 IEEE 12th International Conference on Computer Vision.

[142]  V. Champac,et al.  Delay sensing for long-term variations and defects monitoring in safety–critical applications , 2010, 2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS).

[143]  R. Azevedo,et al.  An efficient framework for high-level power exploration , 2007, 2007 50th Midwest Symposium on Circuits and Systems.

[144]  Yiming Huai,et al.  Spin-Transfer Torque MRAM (STT-MRAM): Challenges and Prospects , 2008 .

[145]  Mircea R. Stan,et al.  Low-power encodings for global communication in CMOS VLSI , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[146]  Roman Obermaisser,et al.  Composability in the time-triggered system-on-chip architecture , 2008, 2008 IEEE International SOC Conference.

[147]  Sharad Malik,et al.  Dynamic power management for microprocessors: a case study , 1997, Proceedings Tenth International Conference on VLSI Design.

[148]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[149]  Lu Wang,et al.  Background Subtraction using Incremental Subspace Learning , 2007, 2007 IEEE International Conference on Image Processing.

[150]  Luca Benini,et al.  Low power error resilient encoding for on-chip data buses , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[151]  Peter Sanders,et al.  Asynchronous scheduling of redundant disk arrays , 2000, SPAA '00.

[152]  David S. Wishart Number of Clusters , 2005 .

[153]  Hermann Kopetz,et al.  The time-triggered architecture , 2003 .

[154]  Kaushik Roy,et al.  A CMOS thermal sensor and its applications in temperature adaptive design , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[155]  Sharad Malik,et al.  Instruction level power analysis and optimization of software , 1996, J. VLSI Signal Process..

[156]  Jacques E. Boillat,et al.  Load Balancing and Poisson Equation in a Graph , 1990, Concurr. Pract. Exp..

[157]  Melvin A. Breuer,et al.  An Illustrated Methodology for Analysis of Error Tolerance , 2008, IEEE Design & Test of Computers.

[158]  Jan M. Rabaey,et al.  Activity-sensitive architectural power analysis , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[159]  R.W. Brodersen,et al.  A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.

[160]  Michael Meitinger,et al.  An Application-Aware Load Balancing Strategy for Network Processors , 2010, HiPEAC.

[161]  Karl Rohnke Silver Bullets , 1984 .

[162]  Sarita V. Adve,et al.  Shared Memory Consistency Models: A Tutorial , 1996, Computer.

[163]  Sudhakar Yalamanchili,et al.  Power constrained design of multiprocessor interconnection networks , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[164]  M. Suzuoki,et al.  Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor , 2006, IEEE Journal of Solid-State Circuits.

[165]  Luca Benini,et al.  Packetization and routing analysis of on-chip multiprocessor networks , 2004, J. Syst. Archit..

[166]  Daisuke Takahashi,et al.  The HPC Challenge (HPCC) benchmark suite , 2006, SC.

[167]  S. D. Chatterji Proceedings of the International Congress of Mathematicians , 1995 .

[168]  George Cybenko,et al.  Dynamic Load Balancing for Distributed Memory Multiprocessors , 1989, J. Parallel Distributed Comput..

[169]  George A. Constantinides,et al.  Methodology for designing statically scheduled application-specific SDRAM controllers using constrained local search , 2009, 2009 International Conference on Field-Programmable Technology.

[170]  Hui Zhang,et al.  Low-swing interconnect interface circuits , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[171]  Wayne H. Wolf,et al.  Multiprocessor Systems-on-Chips , 2004, ISVLSI.

[172]  Kees G. W. Goossens,et al.  Predator: A predictable SDRAM memory controller , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[173]  Lukas Kencl LOAD SHARING FOR MULTIPROCESSOR NETWORK NODES , 2003 .

[174]  Marios C. Papaefthymiou,et al.  HyPE: hybrid power estimation for IP-based programmable systems , 2003, ASP-DAC '03.

[175]  Jan M. Rabaey,et al.  Early power exploration—a World Wide Web application , 1996, DAC '96.

[176]  Jürgen Teich,et al.  Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology , 2006, Int. J. Embed. Syst..

[177]  Kurt Keutzer,et al.  Exploring recognition network representations for efficient speech inference on highly parallel platforms , 2010, INTERSPEECH.

[178]  Fernando Gehm Moraes,et al.  Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs , 2007, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07).

[179]  Jan M. Rabaey,et al.  Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs , 1999, Proceedings. IEEE Computer Society Workshop on VLSI '99. System Design: Towards System-on-a-Chip Paradigm.

[180]  Radu Marculescu,et al.  Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[181]  M. Lustig,et al.  Clinically Feasible Reconstruction Time for L 1-SPIRiT Parallel Imaging and Compressed Sensing MRI , 2009 .

[182]  Massimo Poncino,et al.  MO deling and DE sign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems , 2010 .

[183]  E.J. Candes Compressive Sampling , 2022 .

[184]  R. Engelbrecht,et al.  DIGEST of TECHNICAL PAPERS , 1959 .

[185]  Mohamed Abid,et al.  System Level Design Space Exploration for Multiprocessor System on Chip , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

[186]  Shahriar Mirabbasi,et al.  System-on-Chip: Reuse and Integration , 2006, Proceedings of the IEEE.

[187]  Luciano Lavagno,et al.  Efficient power co-estimation techniques for system-on-chip design , 2000, DATE '00.

[188]  Eleanore Hartson,et al.  Time Out , 1982 .

[189]  Christopher J. Hughes,et al.  Carbon: architectural support for fine-grained parallelism on chip multiprocessors , 2007, ISCA '07.