A New Low Power BIST Architecture Based on Probability Models

BIST(Built-In Self-Test) architecture is proposed for reducing average power consumption during the test procedure. It is the characteristic of the architecture that power reduction is achieved without impact on fault coverage. The proposed architecture contains an additional probability generator module to eliminate transitions and it is based on probability models which are also proposed. Experiments performed on the ISCAS’89 benchmark circuits show that transition reduction during scan testing can be reduced up to 67.77%. The results demonstrate the effectiveness of the architecture as compared with the results of previous works.

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