Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs

Testing for three dimensional (3D) integrated circuits (ICs) based on through-silicon-via (TSV) is one of the major challenges for improving the system yield and reducing the overall cost. The lack of pads on most tiers and the mechanical vulnerability of tiers after wafer thinning make it difficult to perform 3D Known-Good-Die (KGD) test with the existing 2D IC probing methods. This paper presents a novel and time-efficient 3D testing flow. In this Known-Good-Stack (KGS) flow, a yield-aware TSV defect searching and replacing strategy is introduced. The Build-in-Self-Test (BIST) design with TSV redundancy scheme can help improve the system yield for today's imperfect TSV fabrication process. Our study shows that less than 6 redundant TSVs is enough to increase the TSV yield to 98% for a TSV cluster with a size under 16×16 with relatively low initial TSV yield. The average TSV cluster testing and self-fixing time is about 3-16 testing cycle depending on the initial TSV yield.1

[1]  Luca Benini,et al.  Design Issues and Considerations for Low-Cost 3-D TSV IC Technology , 2010, IEEE Journal of Solid-State Circuits.

[2]  Yervant Zorian,et al.  Testing 3D chips containing through-silicon vias , 2009, 2009 International Test Conference.

[3]  Xiaoxia Wu,et al.  Test-access mechanism optimization for core-based three-dimensional SOCs , 2008, 2008 IEEE International Conference on Computer Design.

[4]  Yuan Xie,et al.  Design space exploration for 3D architectures , 2006, JETC.

[5]  Yuan Xie,et al.  Architectural benefits and design challenges for three-dimensional integrated circuits , 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

[6]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[7]  TingTing Hwang,et al.  TSV redundancy: Architecture and design issues in 3D IC , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[8]  Yuan Xie,et al.  System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs) , 2009, 2009 Asia and South Pacific Design Automation Conference.

[9]  Ding-Ming Kwai,et al.  A built-in self-test scheme for the post-bond test of TSVs in 3D ICs , 2011, 29th VLSI Test Symposium.

[10]  Fan Zhang,et al.  Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods , 2012, J. Electron. Test..

[11]  R. Anciant,et al.  Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs , 2010, 2010 IEEE International Interconnect Technology Conference.

[12]  John P. Hayes,et al.  Contactless testing: Possibility or pipe-dream? , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[13]  J. Cluzel,et al.  Investigation on TSV impact on 65nm CMOS devices and circuits , 2010, 2010 International Electron Devices Meeting.