The HtComp Research Project: An Overview

This contribution reviews the main results of the HtComp project, a two-year research programme aiming at facilitating the integration of FPGA-based accelerators into general-purpose computing. The project covered the automated generation of HDL code from parallel applications written in traditional high-level software languages, as well as the customization of the processing, memory, and on-chip interconnect subsystems tailored on the application requirements. The ultimate outcome of the research was the introduction of methods and tools allowing software developers, particularly from the HPC domain, to access hardware-accelerated platforms incurring significantly reduced design complexity and overheads.

[1]  Cédric Bastoul,et al.  Code generation in the polyhedral model is easier than you think , 2004, Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004..

[2]  Nikil D. Dutt,et al.  Constraint-driven bus matrix synthesis for MPSoC , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[3]  Luca Benini,et al.  An Application-Specific Design Methodology for On-Chip Crossbar Generation , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Philippe Coussy,et al.  High-Level Synthesis: from Algorithm to Digital Circuit , 2008 .

[5]  Alessandro Cilardo,et al.  Efficient Bit-Parallel GF(2^m) Multiplier for a Large Class of Irreducible Pentanomials , 2009, IEEE Transactions on Computers.

[6]  Partha Pratim Pande,et al.  Hardware accelerators for biocomputing: A survey , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[7]  Heterogeneous Computing in the Cloud : Crunching Big Data and Democratizing , 2012 .

[8]  Eui-Young Chung,et al.  Partial Connection-Aware Topology Synthesis for On-Chip Cascaded Crossbar Network , 2012, IEEE Transactions on Computers.

[9]  Alessandro Cilardo,et al.  Exploiting Vulnerabilities in Cryptographic Hash Functions Based on Reconfigurable Hardware , 2013, IEEE Transactions on Information Forensics and Security.

[10]  Edoardo Fusella,et al.  Automated synthesis of FPGA-based heterogeneous interconnect topologies , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[11]  Alessandro Cilardo,et al.  Design space exploration for high-level synthesis of multi-threaded applications , 2013, J. Syst. Archit..

[12]  Alessandro Cilardo,et al.  Efficient and scalable OpenMP-based system-level design , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[13]  Alessandro Cilardo,et al.  ASP-based optimized mapping in a simulink-to-MPSoC design flow , 2014, J. Syst. Archit..

[14]  Alessandro Cilardo,et al.  Improving Multibank Memory Access Parallelism with Lattice-Based Partitioning , 2015, ACM Trans. Archit. Code Optim..

[15]  Alessandro Cilardo,et al.  Customizable Heterogeneous Acceleration for Tomorrow's High-Performance Computing , 2015, 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems.

[16]  Alessandro Cilardo,et al.  New Techniques and Tools for Application-Dependent Testing of FPGA-Based Components , 2015, IEEE Transactions on Industrial Informatics.

[17]  Alessandro Cilardo,et al.  Interplay of loop unrolling and multidimensional memory partitioning in HLS , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[18]  Edoardo Fusella,et al.  Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects , 2015, ACM Trans. Embed. Comput. Syst..

[19]  Eric S. Chung,et al.  A reconfigurable fabric for accelerating large-scale datacenter services , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).