FPGA and ASIC realisation of EMD algorithm for real-time signal processing

In this study, the authors have proposed both field-programmable gate array (FPGA) and application specific integrated circuit (ASIC) based realisation of the empirical mode decomposition (EMD) algorithm for the real-time signal processing. Here, a single module is used for the calculation of maxima and minima, and another single module is used for the calculation of upper and lower envelopes instead of using separate modules for each calculation. In this work, the traditional cubic spline interpolation has been replaced with sawtooth transform followed by a smoothing module called moving average. In this study firstly, Verilog-HDL code for the EMD is written using Xilinx Vivado and tested in the simulation phase, later dumped into Digilentinc Basys 3 FPGA board to do the hardware verification. For ASIC, the code is synthesised using Cadence Genus tool with the semi-conductor laboratory 180 nm cell library and the layout is made in the Cadence Innovus tool. The proposed EMD can work with a clock/sampling rate up to 25 MHz and has a layout area of 3.9 mm 2 . For the reduction of power consumption of the overall system, clock gating has been used which helps to reduce the dynamic power of the modules, when they are not in use.

[1]  Po-Lei Lee,et al.  Hardware Implementation of EMD Using DSP and FPGA for Online Signal Processing , 2011, IEEE Transactions on Industrial Electronics.

[2]  N. Huang,et al.  The empirical mode decomposition and the Hilbert spectrum for nonlinear and non-stationary time series analysis , 1998, Proceedings of the Royal Society of London. Series A: Mathematical, Physical and Engineering Sciences.

[3]  Mohammed Imamul Hassan Bhuiyan,et al.  Detection of Seizure and Epilepsy Using Higher Order Statistics in the EMD Domain , 2013, IEEE Journal of Biomedical and Health Informatics.

[4]  Ram Bilas Pachori,et al.  Classification of Seizure and Nonseizure EEG Signals Using Empirical Mode Decomposition , 2012, IEEE Transactions on Information Technology in Biomedicine.

[5]  Ying-Yi Hong,et al.  FPGA Implementation for Real-Time Empirical Mode Decomposition , 2012, IEEE Transactions on Instrumentation and Measurement.

[6]  Carmine Landi,et al.  Power-Quality Monitoring Instrument With FPGA Transducer Compensation , 2009, IEEE Transactions on Instrumentation and Measurement.

[7]  Yusuf Yaslan,et al.  Empirical mode decomposition based denoising method with support vector regression for time series prediction: A case study for electricity load forecasting , 2017 .

[8]  Ram Bilas Pachori,et al.  Analysis of normal and epileptic seizure EEG signals using empirical mode decomposition , 2011, Comput. Methods Programs Biomed..

[9]  Hong Fan,et al.  Rotating machine fault diagnosis using empirical mode decomposition , 2008 .

[10]  S. Snelgrove,et al.  Medication Monitoring for People with Dementia in Care Homes: The Feasibility and Clinical Impact of Nurse-Led Monitoring , 2014, TheScientificWorldJournal.

[11]  Klaus D. McDonald-Maier,et al.  FPGA-Based Real-Time Implementation of Bivariate Empirical Mode Decomposition , 2019, Circuits Syst. Signal Process..

[12]  Pei-Yin Chen,et al.  Hardware Design and Implementation for Empirical Mode Decomposition , 2016, IEEE Transactions on Industrial Electronics.

[13]  Kim Dremstrup,et al.  EMD-Based Temporal and Spectral Features for the Classification of EEG Signals Using Supervised Learning , 2016, IEEE Transactions on Neural Systems and Rehabilitation Engineering.

[14]  Wen-Chung Shen,et al.  New Ping-Pong Scheduling for Low-Latency EMD Engine Design in Hilbert–Huang Transform , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[15]  S. S. Shen,et al.  A confidence limit for the empirical mode decomposition and Hilbert spectral analysis , 2003, Proceedings of the Royal Society of London. Series A: Mathematical, Physical and Engineering Sciences.