Directed self-assembly for ever-smaller printed circuits

Field effect transistors (FETs) composed of discrete silicon (Si) active regions or ‘fins,’ referred to as finFETs, have superior electrostatic properties compared to planar devices (see Figure 1).1 As a result, they are likely to play a role in further miniaturization of electronic devices.2 However, density requirements for fin patterning have exceeded what can be achieved through direct printing by 193nm immersion (193i) lithography. Consequently, sublithographic patterning techniques that can extend the resolution of 193i to the sub-80nm pitch regime (i.e., where the distance between identical features is less than 80nm) are now of vital importance. Sidewall image transfer (SIT) is now commonly used to manufacture 22nm-node finFET-based technology (meaning the transistor is 22nm across).2 The SIT process doubles the spatial frequency of a template or mandrel shape printed by a conventional lithography through a sequential deposition and etch process. This forms a feature along the sidewalls of the template shape similar to an offset spacer in a CMOS transistor. By removing the template shape selectively, the remaining sidewall features can be used for further pattern transfer. Coupled with 193i, SIT can be used to fabricate grating-like features with a minimum full pitch of 40nm. A further lithography step can be used to customize the grating pattern into a circuit pattern provided it obeys certain design rule restrictions determined by the SIT process. Extending SIT to the sub-40nm pitch regime requires us to reduce the template pitch to less than 80nm. This can be achieved using multiple interleaved 193i exposures or a higher resolution lithography, such as extreme ultraviolet or electron beam lithography. Another option is to perform a further iteration of the SIT process, resulting in a tripling or quadrupling of pitch. While these approaches can all lead to finer pitch patterning, Figure 1. A 3D schematic of a finFET device. Because the gate wraps around the channel region between source and drain of a finFET, the same level of gate control can be achieved with a shorter gate length. Dfin: Fin width. Hfin: Fin height. Lg: Gate length.