Macromodels for Static Virtual Ground Voltage Estimation in Power-Gated Circuits
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[1] Olivier Sentieys,et al. A semiempirical model for wakeup time estimation in power-gated logic clusters , 2012, DAC Design Automation Conference 2012.
[2] Bharadwaj S. Amrutur,et al. Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization , 2008, 21st International Conference on VLSI Design (VLSID 2008).
[3] Andrew McCallum,et al. Toward Optimal Active Learning through Sampling Estimation of Error Reduction , 2001, ICML.
[4] Burr Settles,et al. Active Learning Literature Survey , 2009 .
[5] Daphne Koller,et al. Support Vector Machine Active Learning with Applications to Text Classification , 2000, J. Mach. Learn. Res..
[6] Johan A. K. Suykens,et al. Least Squares Support Vector Machine Classifiers , 1999, Neural Processing Letters.
[7] Kevin J. Nowka,et al. Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[8] V. Sahula,et al. Variability aware support vector machine based macromodels for statistical estimation of subthreshold leakage power , 2012, 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).
[9] Ranga Vemuri,et al. Dynamic Characteristics of Power Gating During Mode Transition , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[10] Saibal Mukhopadhyay,et al. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.