Design of a Stable Low Power 11-T Static Random Access Memory Cell

In this paper, a 11-T static random-access memory (SRAM) cell has been examined that shows a fair reduction in read power dissipation while upholding the stability and moderate performance. In the ...

[1]  Soumitra Pal,et al.  Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Kaushik Roy,et al.  A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[3]  Sakti Prasad Ghoshal,et al.  A Design of Highly Stable and Low-Power SRAM Cell , 2018, Advances in Intelligent Systems and Computing.

[4]  Neeta Pandey,et al.  A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Mohd. Hasan,et al.  Low Leakage Single Bitline 9 T (SB9T) Static Random Access Memory , 2017, Microelectron. J..

[6]  Jan M. Rabaey,et al.  Standby supply voltage minimization for deep sub-micron SRAM , 2005, Microelectron. J..

[7]  R. S. Gamad,et al.  A data-aware write-assist 10T SRAM cell with bit-interleaving capability , 2018, Turkish J. Electr. Eng. Comput. Sci..

[8]  E. Nowak,et al.  Low-power CMOS at Vdd = 4kT/q , 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).

[9]  Rajesh A. Thakker,et al.  Characterization of a novel 10T SRAM cell with improved data stability and delay performance for 20-nm tri-gated FinFET technology , 2018, Circuit World.

[10]  A. Wang,et al.  Modeling and sizing for minimum energy operation in subthreshold circuits , 2005, IEEE Journal of Solid-State Circuits.

[11]  Yong Li,et al.  Differential-read 8T SRAM cell with tunable access and pull-down transistors , 2012 .

[12]  Shi-Yu Huang,et al.  P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation , 2011, IEEE Journal of Solid-State Circuits.

[13]  S. Roy,et al.  The impact of random doping effects on CMOS SRAM cell , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[14]  Ruchi,et al.  6T SRAM cell analysis for DRV and read stability , 2017 .

[15]  Santosh Kumar Vishvakarma,et al.  Stable, Reliable, and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-Design , 2017, IEEE Transactions on Semiconductor Manufacturing.

[16]  P. Arun,et al.  Optimization of SnS active layer thickness for solar cell application , 2017 .

[17]  Behzad Ebrahimi,et al.  A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies , 2015, Integr..

[18]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[19]  Sakti Prasad Ghoshal,et al.  A design of low swing and multi threshold voltage based low power 12T SRAM cell , 2015, Comput. Electr. Eng..

[20]  Ajay Kumar Singh,et al.  Novel Eight-Transistor SRAM cell for write power reduction , 2010, IEICE Electron. Express.

[21]  Farshad Moradi,et al.  A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology , 2014, Microelectronics Journal.

[22]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[23]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[24]  Zhiyu Liu,et al.  Characterization of a Novel Nine-Transistor SRAM Cell , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[25]  Mohd. Hasan,et al.  Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  Ping Keung Ko,et al.  A MOSFET electron mobility model of wide temperature range (77 - 400 K) for IC simulation , 1997 .

[27]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[28]  S. Chouhan,et al.  A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications , 2018, Analog Integrated Circuits and Signal Processing.

[29]  Yong Li,et al.  Single-ended, robust 8T SRAM cell for low-voltage operation , 2013, Microelectron. J..

[30]  Sied Mehdi Fakhraie,et al.  An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs , 2014, IEEE Transactions on Electron Devices.

[31]  Sudeb Dasgupta,et al.  Process Corners Analysis of Data Retention Voltage (DRV) for 6T, 8T, and 10T SRAM Cells at 45 nm , 2019 .