Design of a 64 channel analog receive beamformer for high frequency linear arrays

A new 64 channel analog receive beamformer was developed to support a recently built 30 MHz 256-element linear array with 50 μm pitch. Each channel of the proposed beamformer consisted of a coarse delay and a fine delay circuit block. The delay blocks were implemented using wide bandwidth tapped delay lines. Multiplexers were used to select the output taps of the fine delay and coarse delay. Field Programmable Gate Arrays (FPGA) devices which stored the delay profile of each channel were used to update the control signals for the multiplexers at each scan line and focal zone switching. Due to the transient effect when turning a switch on or off, glitch noise could be introduced during each focal zone transition. A differential circuit, as well as switch offsetting, was used to suppress such an effect. The design was shown to be capable of providing a total delay of 157 ns with a resolution of 1ns. The rise time of the cascading delay lines was 8.66 ns, which set the −3dB bandwidth to about 40MHz. The test on two channels of the beamformer showed a 20 dB improvement in SNR by the two glitch suppressing methods. Phantoms images shows that the system can achieve lateral resolution of 120 μm, and can resolve anechoic spheres as small as 300 μm in diameter.