Compact modelling of noise for RF CMOS circuit design

The thermal noise of short-channel NMOS transistors in a commercially available 0.13 -mm CMOS technology is studied. The experimental results are modelled with a non-quasi- static RF model, based on the principle of channel segmentation. The model is capable of predicting both drain and gate current noise accurately, without fitting any parameters to the measured noise data. An essential ingredient of the model is the gate resistance, which is shown to dominate the gate current noise. In the optimised device layouts, this gate resistance is mainly determined by the silicide-to-polysilicon contact resistance. The ever-continuing downscaling of CMOS technologies has resulted in a strong improvement in the RF perfor- mance of MOS devices (1-3). Consequently, CMOS has become a viable option for analogue RF applications and RF system-on-chip. For the application of modern CMOS technologies in low-noise RF circuits, accurate modelling of noise is a prerequisite. In MOSFETs, there are two intrinsic sources of noise: 1/f noise and thermal noise, the latter being the topic of this paper. Thermal noise is due to the random thermal motion of charge carriers. It not only manifests itself in the drain current noise spectrum, but, due to the capacitive coupling between channel and gate, also in the gate current noise spectrum. The latter effect is known as 'induced gate noise'. In addition to the intrinsic MOSFET thermal noise, the parasitic resistances (gate resistance, bulk resistance, and source/drain resistances) also exhibit thermal noise. Thermal noise of deep-submicron MOSFETs has received considerable attention lately, triggered by publica- tions reporting a strong enhancement of thermal noise with respect to long-channel theory (4-8). In the earliest of these publications (4), thermal noise was found to be enhanced by a factor upto 12 in n-channel devices with gate length 0.7mm, and hot electrons were proposed to explain these results. More recently, Klein (5, 6) reported very similar enhancement of drain current thermal noise in devices with gate length 0.65mm and proposed a model that invokes heating of the charge carriers in the inversion channel to explain the experiments. For the induced gate noise, an even more dramatic enhancement factor as large as 30 was found by Knoblinger (7) for a 0.25 -mm gate length n-channel MOSFET. Evidently, these reported noise enhancements would seriously limit the viability of RF CMOS, and a detailed study is called for. In previous work (9-11), in sharpcontrast to the above- mentioned authors, only moderate enhancement of the MOSFET drain current thermal noise was found, mainly caused by parasitic resistances and channel length modula- tion. This was found for 0.35 -mm, 0.25 -mm, and 0.18 -mm CMOS technologies. MOSFET gate current thermal noise, on the other hand, was found to be enhanced more severely. This enhancement could be traced back to the effects of gate resistance, and the silicide-to-polysilicon contact resistance in particular. Although the thermal noise, as found in CMOS fabrication down to 0.18mm, seems fairly well understood, it remains important to study the phenomenon for more advanced CMOS technologies: it seems probable that at some point down the ITRS roadmap, the main assumption of our theory, i.e. thermal equilibrium, will break down. Therefore, in this work (which was reported earlier in (12)), we extend our study of MOSFET thermal noise to 0.13 -mm technology. We present a large number of new experimental results in the 1-18 GHz frequency range, and compare them with the predictions of our previously developed RF MOSFET model.

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