An Energy-Efficient 13-bit Zero-Crossing ΔΣ Capacitance-to-Digital Converter with 1 pF-to-10 nF Sensing Range
暂无分享,去创建一个
Wei Wang | Chuang Li | Qian Yang | Bing Li | Jia Liu | Wen-Jun Liu | Wen Bin Ye
[1] Khaled N. Salama,et al. A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.
[2] Kong-Pang Pun,et al. A High-Linearity Capacitance-to-Digital Converter Suppressing Charge Errors From Bottom-Plate Switches , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.
[3] Hae-Seung Lee,et al. A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC , 2009, IEEE Journal of Solid-State Circuits.
[4] L. Benini,et al. CMOS DNA Sensor Array With Integrated A/D Conversion Based on Label-Free Capacitance Measurement , 2006, IEEE Journal of Solid-State Circuits.
[5] David Blaauw,et al. A Dual-Slope Capacitance-to-Digital Converter Integrated in an Implantable Pressure-Sensing System , 2014, IEEE Journal of Solid-State Circuits.
[6] Nan Sun,et al. An Energy-Efficient Hybrid SAR-VCO $\Delta \Sigma $ Capacitance-to-Digital Converter in 40-nm CMOS , 2017, IEEE Journal of Solid-State Circuits.