Shared-memory optical packet (ATM) switch

Previously, we determined fundamental performance limitations associated with `all-optical' packet switches, in which the packet buffering is implemented via fiber delay lines. In this work, we propose and analyze an optical packet (ATM) switch architecture that comes close to achieving the optimal performance (i.e., best possible delay-throughput performance and minimal possible buffer requirements) of a random-access, shared-memory design. The proposed Shared-Memory Optical Packet (SMOP) Switch buffers packets in recirculation delay lines of appropriately-selected lengths, and uses a novel control algorithm that: (i) keeps packets in their proper first-in, first-out sequence, (ii) supports multiple levels of priority traffic, (iii) minimizes the needed number of recirculation loops (which reduces the size of the switch fabric), and (iv) ensures that packets pass through the recirculation delay lines only a small number of times (e.g., less than 10).