Design of an interlayer deblocking filter architecture for H.264/SVC based on a novel sample-level filtering order

This paper presents the architectural design for an interlayer Deblocking Filter of the H.264/SVC standard. The architecture described applies a novel and efficient processing order based on sample-level filterings. This order allows a better exploration of the filter parallelism, decreasing in 25% the number of cycles used to filter the videos, when compared to the best related work. Four concurrent filter cores were used in the architecture, which was described in VHDL and synthesized for an Altera Stratix III FPGA device. The timing analysis results showed that this design is able to filter up to 130 HDTV (1920×1080 pixels) frames per second.

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