Low leakage write-enhanced robust 11T SRAM cell with fully half-select-free operation

SRAM circuit design faces new challenges, mainly high leakage power and stability issue in modern scaled technology. This work proposed a new low leakage fully half-select-free robust 11T SRAM cell, which eliminates read disturb and significantly improves the write performance by using power cut-off and write ‘0’ only technique. It also avoids the floating-VDD situation of storage nodes as encountered in earlier power cut-off cells. The proposed cell offers 23.8% and 37.4% improvement in the effective mean of RSNM and WM as compared with existing 11T cell (at VDD=0.5V). At the same supply voltage, it also reduces the leakage power by 35% and 12% as compared with 6T and existing 11T cell. Therefore, the proposed cell could be a good choice for applications that demands high stability and low power and can also be implemented in bit-interleaving architecture to achieve soft error immunity with error correction code (ECC).

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