Applying Machine Learning to Design for Reliability Coverage

Large integrated circuits, such as System-on-a-Chip (SoC) designs, often suffer from a reduced operational frequency due to various timing constraints. This reduction in operating frequency is often caused by the impact of dynamic voltage drop or aging/thermal on setup timing violations, often referred to as maximum timing pushout. This problem is exacerbated in advanced FinFET designs such as 7nm/5nm due to reduced VDD, insufficient switching scenario coverage, increased resistance of lower layers of metal, and larger local power density. This paper proposes a novel method using machine learning techniques to design for reliability coverage by using critical scenario(s) predictor for running dynamic voltage drop analysis and critical timing path(s) predictor for accurate timing/aging analysis with impact of voltage drop.