An 11mW continuous time delta-Sigma modulator with 20 MHz bandwidth in 65nm CMOS

This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock jitter sensitivity. The measured prototype consumes 11mW from a 1.2 V power supply, and achieves an SNDR/SFDR of 63.5dB/76dB.

[1]  Pietro Andreani,et al.  A 7.5mW 9MHz CT ΔΣ modulator in 65nm CMOS with 69 dB SNDR and reduced sensitivity to loop delay variations , 2012, 2012 IEEE Asian Solid State Circuits Conference (A-SSCC).

[2]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[3]  A. Torralba,et al.  A 4.7mW 89.5dB DR CT complex /spl Delta//spl Sigma/ ADC with built-in LPF , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[4]  Shanthi Pavan,et al.  Design Techniques for Wideband Single-Bit Continuous-Time $\Delta\Sigma$ Modulators With FIR Feedback DACs , 2012, IEEE Journal of Solid-State Circuits.

[5]  Mohammad Ranjbar,et al.  Continuous-time feed-forward ΣΔ- modulators with robust signal transfer function , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[6]  Shanthi Pavan,et al.  Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.