Estimation of energy consumption in speed-independent control circuits

We describe a technique to estimate the energy consumed by speed-independent asynchronous (clock-less) control circuits. Because speed-independent circuits are hazard-free under all possible combi- nations of gate delays+ we prove that an accurate estimate of their energy consumption is independent of relative component gate delays and can be determined by simulating only a small number of input patterns proportional to the size of the circuit's Signal Transition Graph specification. Specifically, we calculate the average energy per extemnl signal transition consumed by a circuit. This can be used to compare the energy consumption between two different circuit implementations of the same specification, to calculate average energy for a given high- level operation, and to provide average circuit power when combined with delay information,

[1]  Alexandre Yakovlev,et al.  Signal Graphs: From Self-Timed to Timed Ones , 1985, PNPM.

[2]  Kurt Keutzer,et al.  Estimation of average switching activity in combinational and sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[3]  Tam-Anh Chu,et al.  Synthesis of self-timed VLSI circuits from graph-theoretic specifications , 1987 .

[4]  Bill Lin,et al.  Synthesis of concurrent system interface modules with automatic protocol conversion generation , 1994, ICCAD.

[5]  Antti Valmari,et al.  A stubborn attack on state explosion , 1990, Formal Methods Syst. Des..

[6]  Farid N. Najm,et al.  Transition density, a stochastic measure of activity in digital circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[7]  Ivan E. Sutherland,et al.  Micropipelines , 1989, Commun. ACM.

[8]  Chi-Ying Tsui,et al.  Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs , 1994, 31st Design Automation Conference.

[9]  Luciano Lavagno,et al.  Synthesis and Testing of Bounded Wire Delay Asynchronous Circuits from Signal Transition Graphs , 1992 .

[10]  Pierre Wolper,et al.  Using partial orders for the efficient verification of deadlock freedom and safety properties , 1991, Formal Methods Syst. Des..

[11]  Teresa H. Y. Meng,et al.  Automatic gate-level synthesis of speed-independent circuits , 1992, ICCAD '92.

[12]  Alain J. Martin Programming in VLSI: from communicating processes to delay-insensitive circuits , 1991 .

[13]  Ken Stevens,et al.  The Post Office experience: designing a large asynchronous chip , 1993, Integr..

[14]  Peter A. Beerel CAD tools for the synthesis, verification, and testability of robust asynchronous circuits , 1995 .

[15]  Teresa H. Y. Meng,et al.  Semi-modularity and testability of speed-independent circuits , 1992, Integr..

[16]  Antti Valmari A stubborn attack on state explosion , 1992, Formal Methods Syst. Des..

[17]  Venkatesh Akella,et al.  A technique for estimating power in asynchronous circuits , 1994, Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems.

[18]  Luciano Lavagno,et al.  Algorithms for synthesis of hazard-free asynchronous circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[19]  Teresa H. Y. Meng,et al.  Sufficient conditions for correct gate-level speed-independent circuits , 1994, Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems.

[20]  R. Marculescu,et al.  Switching Activity Analysis Considering Spatioternporal Correlations , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[21]  Sheldon M. Ross,et al.  Introduction to probability models , 1975 .