FPGA implementation of authenticated encryption algorithm Minalpher
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A new authenticated encryption algorithm Minalpher [1] submitted to CAESAR (Competition for Authenticated Encryption: Security, Applicability, and Robustness) [2] was implemented on various FPGA devices with straightforward and pipelined hardware architectures. Then, its performances in operating speed, hardware size, and power consumption were compared with a current standard algorithm AES-GCM [3] to show the advantages of Minalpher in compact and high-speed hardware implementations.
[1] Akashi Satoh,et al. High-Performance Hardware Architectures for Galois Counter Mode , 2009, IEEE Transactions on Computers.
[2] D. McGrew,et al. The Galois/Counter Mode of Operation (GCM) , 2005 .