Scalable Hardware-Algorithms for Binary Prefix Sums

The main contribution of this work is to propose a number of broadcast-efficient VLSI architectures for computing the sum and the prefix sums of a ω κ -bit, κ > 2, binary sequence using, as basic building blocks, linear arrays of at most ω 2 shift switches. An immediate consequence of this feature is that in our designs broadcasts are limited to buses of length at most ω 2 making them eminently practical. Using our design, the sum of a ω κ -bit binary sequence can be obtained in the time of 2κ-2 broadcasts, using 2ω κ-2 + O(ω κ-3 ) blocks, while the corresponding prefix sums can be computed in 3k - 4 broadcasts using (κ + 2)ω κ-2 + O(κω κ-3 ) blocks.