Synthesis for testability by sequential redundancy removal using retiming

The existence of sequential redundancy degrades testability of sequential circuits. By using retiming which rearranges flip-flops, some sequential redundancy is converted into combinational redundancy, which can be easily identified and removed by a combinational test generation technique. Retiming is utilized for two purposes: one is for finding sequential redundancy and another is for reducing the number of flip-flops. Applying retiming and redundancy removal techniques concurrently, testability of sequential circuits is enhanced. Experimental results for ISCAS'89 benchmark circuits show the effectiveness of this method for optimizing circuits.<<ETX>>

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