论文信息 - Design of Cache Test Hardware on the HP PA8500 - 字舞流文

Design of Cache Test Hardware on the HP PA8500

Refinements to testing strategies for earlier microprocessor on-chip caches led to fast, efficient characterization and debugging of the smaller geometry PA8500 cache.

Jeff Brauch | Jay Fleischman

[1] Ion M. Ratiu,et al. Pseudorandom Built-in Self-Test Methodology and Implementation for the IBM RISC System/6000 Processor , 1990, IBM J. Res. Dev..

[2] Sridhar Narayanan,et al. Testability, debuggability, and manufacturability features of the UltraSPARC-I microprocessor , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[3] René David,et al. Random Pattern Testing Versus Deterministic Testing of RAM's , 1989, IEEE Trans. Computers.

[4] A. J. van de Goor,et al. Testing Semiconductor Memories: Theory and Practice , 1998 .

[5] Ad J. van de Goor,et al. Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..

[6] Georgi Gaydadjiev,et al. March LR: a test for realistic linked faults , 1996, Proceedings of 14th VLSI Test Symposium.

[7] Bruce F. Cockburn,et al. Detection of coupling faults in RAMs , 1990, J. Electron. Test..