DECOUPLE: defect current detection in deep submicron I/sub DDQ/

I/sub DDQ/ test concept for deep submicron (DSM) devices named DECOUPLE (Defect Current Observation Under the Proportion of intrinsic Leakage currents) is proposed. A new clustering method obtained two defect free groups from a production data set by abstracting from a signature of intrinsic leakage current that is independent of process variations. Possible pass/fail tests, diagnosis, and detection of parametric defect currents are discussed on the data set. Another example of the pass/fail tests on a second product is presented.

[1]  Manoj Sachdev.  Deep Sub-micron IDDQ Test Options , 1996 .

[2]  Kaushik Roy,et al.  Intrinsic leakage in low power deep submicron CMOS ICs , 1997, Proceedings International Test Conference 1997.

[3]  Franco Motika,et al.  Application and analysis of IDDQ diagnostic software , 1997, Proceedings International Test Conference 1997.

[4]  Jerry M. Soden,et al.  High resolution I/sub DDQ/ characterization and testing-practical issues , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[5]  Wojciech Maly,et al.  Toward understanding "Iddq-only" fails , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[6]  Ali Keshavarzi,et al.  Reliabilty, Test, and IDDQ Measurements , 1997 .

[7]  Paul C. Wiscombe,et al.  A comparison of stuck-at fault coverage and I/sub DDQ/ testing on defect levels , 1993, Proceedings of IEEE International Test Conference - (ITC).

[8]  J.W. Slotboom,et al.  Impact of silicon substrates on leakage currents , 1983, IEEE Electron Device Letters.

[9]  Anura P. Jayasumana,et al.  Clustering based techniques for I/sub DDQ/ testing , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[10]  H. Mizuno,et al.  A 18 /spl mu/A-standby-current 1.8 V 200 MHz microprocessor with self substrate-biased data-retention mode , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[11]  Jeff Rearick,et al.  Estimation of defect-free IDDQ in submicron circuits using switch level simulation , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[12]  Charles F. Hawkins,et al.  Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs , 1986, ITC.

[13]  Claude Thibeault.  On the Comparison of IDDQ and IDDQ Testing , 1999, VTS.

[14]  Joan Figueras,et al.  On estimating bounds of the quiescent current for I/sub DDQ/ testing , 1996, Proceedings of 14th VLSI Test Symposium.

[15]  Robert C. Aitken,et al.  Current ratios: a self-scaling technique for production IDDQ testing , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[16]  Wojciech Maly,et al.  Current signatures [VLSI circuit testing] , 1996, Proceedings of 14th VLSI Test Symposium.

[17]  Y. Okuda,et al.  Defect level prediction for I/sub DDQ/ testing , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[18]  Mark C. Johnson,et al.  Models and algorithms for bounds on leakage in CMOS circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Charles F. Hawkins,et al.  Deep Submicron CMOS Current IC Testing: Is There a Future? , 1999, IEEE Des. Test Comput..

[20]  Anthony C. Miller.  I/sub DDQ/ testing in deep submicron integrated circuits , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[21]  F. Joel Ferguson,et al.  Sandia National Labs , 2022 .

[22]  A. Keshavarzi,et al.  Reliability, test, and I/sub DDQ/ measurements , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.