Designs for reducing test time of distributed small embedded SRAMs

This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (e-SRAMs). This architecture improves the one proposed in (W. B. Jone et al, Proc. 17th IEEE VLSI Test Symp., p.246- 251, 1999 and also IEEE Transact. VLSI Syst., vol.10, no.4, p.512-515, 2002). The improvements are mainly two-fold. On one hand, the testing of time-consuming data retention faults (DRFs), that is neglected by the previously proposed test architecture, is now considered and performed via a DFT technique referred to as the "no write recovery test mode (XWRTM)". On the other hand, a parallel local response analyzer (LRA), instead of a serial response analyzer, is used to reduce the test time of these distributed small e-SRAMs. Results from our evaluations show that the proposed test architecture can achieve a better defect coverage and test time compared to those obtained previously, with a negligible area cost.

[1]  Cheng-Wen Wu,et al.  RAMSES: a fast memory fault simulator , 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

[2]  Benoit Nadeau-Dostie,et al.  Serial interfacing for embedded-memory testing , 1990, IEEE Design & Test of Computers.

[3]  Yervant Zorian,et al.  Reducing embedded SRAM test time under redundancy constraints , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[4]  Wen-Ben Jone,et al.  An efficient BIST method for small buffers , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[5]  Chua-Chin Wang,et al.  High fan-in dynamic CMOS comparators with low transistor count , 2003 .

[6]  Yervant Zorian,et al.  Embedded-memory test and repair: infrastructure IP for SoC yield , 2003, IEEE Design & Test of Computers.

[7]  Wen-Ben Jone,et al.  An efficient BIST method for non-traditional faults of embedded memory arrays , 2003, IEEE Trans. Instrum. Meas..

[8]  Wen-Ben Jone,et al.  A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Doe Hyun Yoon,et al.  Dynamic power supply current testing for open defects in CMOS SRAMs , 2001 .

[10]  André Ivanov,et al.  Open defects detection within 6T SRAM cells using a No Write Recovery Test Mode , 2004, 17th International Conference on VLSI Design. Proceedings..

[11]  Wen-Ben Jone,et al.  An efficient BIST method for distributed small buffers , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Jitendra Khare,et al.  Test and debug of networking SoCs-a case study , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[13]  Shi-Yu Huang,et al.  A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters , 2001, Proceedings 10th Asian Test Symposium.

[14]  V. Avendano,et al.  Bit line sensing strategy for testing for data retention faults in CMOS SRAMs , 2000 .

[15]  Marian Marinescu,et al.  Simple and Efficient Algorithms for Functional RAM Testing , 1982, ITC.

[16]  B. Nadeau-Dostie,et al.  A serial interfacing technique for built-in and external testing of embedded memories , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[17]  A. Meixner,et al.  Weak Write Test Mode: an SRAM cell stability design for test technique , 1996, Proceedings International Test Conference 1997.

[18]  Víctor H. Champac,et al.  I/sub DDQ/ testing of opens in CMOS SRAMs , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[19]  Víctor H. Champac,et al.  IDDQ Testing of Opens in CMOS SRAMs , 1999, J. Electron. Test..