Design of a 2 Gb/s transceiver at 60 GHz with integrated antenna in bulk CMOS technology

This work presents the design of a 60 GHz OOK transceiver, with on-chip integrated antenna, for multi Gbit short-range wireless communication. A 65 nm bulk CMOS technology has been selected as target to prove that high-speed fully-integrated RF transceivers can be realized also with low cost digital technologies, suited for wireless consumer applications. The OOK modulation scheme allows for low complex transceiver architecture with all passive and active devices integrated on-chip. At TX side the power stage combines two class-A power amplifiers in a pseudo differential scheme, each made up of a 2 stage Common Source topology with a GT gain of 6.8 dB and a OP1dB of 8.2 dBm. The whole transmitter allows for an output power of about 11 dBm. The antenna is integrated on-chip adopting an half-wavelength dipole topology. Simulated results are a radiation efficiency of 38% and a gain of -1.76 dBi. At RX side a single-stage cascode LNA with a GT gain of 11.46 dB and a noise figure (NF) of 4.69 dB is followed by an OOK demodulator realized with a simple envelope detector. Since both antenna and LNA are integrated on-chip, the impedance matching is not constrained to a 50 Ω value, but its value can be tuned to find an optimal trade-off between NF and gain of the receiver. Combining the proposed RF transceiver with the use of Reed-Solomon channel coding in the digital baseband a data link with an effective data rate of 2 Gb/s can be implemented; the BER is less than 10-5 and 10-12 at 2 m and 1.1 m distance respectively.1