Multipartite table methods

A unified view of most previous table-lookup-and-addition methods (bipartite tables, SBTM, STAM, and multipartite methods) is presented. This unified view allows a more accurate computation of the error entailed by these methods, which enables a wider design space exploration, leading to tables smaller than the best previously published ones by up to 50 percent. The synthesis of these multipartite architectures on Virtex FPGAs is also discussed. Compared to other methods involving multipliers, the multipartite approach offers the best speed/area tradeoff for precisions up to 16 bits. A reference implementation is available at http://www.ens-lyon.fr/LIP/Arenaire/.

[1]  Weng-Fai Wong,et al.  Fast Evaluation of the Elementary Functions in Single Precision , 1995, IEEE Trans. Computers.

[2]  Fred J. Taylor,et al.  A 20 Bit Logarithmic Number System Processor , 1988, IEEE Trans. Computers.

[3]  Javier D. Bruguera,et al.  Faithful powering computation using table look-up and a fused accumulation tree , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[4]  J.-M. Muller,et al.  A new scheme for table-based evaluation of functions , 2002, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002..

[5]  Debjit Das Sarma,et al.  Faithful bipartite ROM reciprocal tables , 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

[6]  Arnaud Tisserand,et al.  Some improvements on multipartite table methods , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[7]  Jean-Michel Muller,et al.  Elementary Functions: Algorithms and Implementation , 1997 .

[8]  J. Detrey,et al.  A VHDL library of LNS operators , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.

[9]  Naofumi Takagi,et al.  Function evaluation by table look-up and addition , 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

[10]  Jean-Michel Muller.  A Few Results on Table-Based Methods , 1998, SCAN.

[11]  Jirí Kadlec,et al.  Arithmetic on the European Logarithmic Microprocessor , 2000, IEEE Trans. Computers.

[12]  Florent de Dinechin,et al.  Multipartite tables in jbits for the evaluation of functions on FPGAs , 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

[13]  Michael J. Schulte,et al.  Approximating Elementary Functions with Symmetric Bipartite Tables , 1999, IEEE Trans. Computers.

[14]  David M. Lewis.  An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System , 1990, IEEE Trans. Computers.

[15]  David W. Matula.  Improved table lookup algorithms for postscaled division , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[16]  David W. Matula,et al.  Analysis of Reciprocal and Square Root Reciprocal Instructions in the AMD K6-2 Implementation of 3DNow! , 1999, Electron. Notes Theor. Comput. Sci..

[17]  Neil Burgess,et al.  A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA , 2003, FPL.

[18]  Michael J. Schulte,et al.  The Symmetric Table Addition Method for Accurate Function Approximation , 1999, J. VLSI Signal Process..