Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams
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Zainalabedin Navabi | Bijan Alizadeh | Pejman Lotfi-Kamran | Mohammad Alisafaee | Saeed Shamshiri | Arash Hooshmand | Mostafa Naderi
[1] Zhihong Zeng,et al. Taylor expansion diagrams: a compact, canonical representation with applications to symbolic verification , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[2] Edward P. Stabler,et al. Parallel implementation of BDD algorithms using a distributed shared memory , 1994, 1994 Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences.
[3] Wolfgang Rosenstiel,et al. Multilevel logic synthesis based on functional decision diagrams , 1992, [1992] Proceedings The European Conference on Design Automation.
[4] Zhihong Zeng,et al. Taylor expansion diagrams: a new representation for RTL verification , 2001, Sixth IEEE International High-Level Design Validation and Test Workshop.
[5] E.M. Clarke,et al. Hybrid decision diagrams. Overcoming the limitations of MTBDDs and BMDs , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[6] Randal E. Bryant,et al. Efficient implementation of a BDD package , 1991, DAC '90.
[7] Rolf Drechsler,et al. The K*BMD: A Verification Data Structure , 1997, IEEE Des. Test Comput..
[8] E BryantRandal. Graph-Based Algorithms for Boolean Function Manipulation , 1986 .
[9] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[10] Enrico Macii,et al. Algebraic decision diagrams and their applications , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[11] Priyank Kalla,et al. High-level design verification using Taylor Expansion Diagrams: first results , 2002, Seventh IEEE International High-Level Design Validation and Test Workshop, 2002..
[12] Forrest Brewer,et al. Implementation of an efficient parallel BDD package , 1996, DAC '96.
[13] Randal E. Bryant,et al. Verification of Arithmetic Circuits with Binary Moment Diagrams , 1995, 32nd Design Automation Conference.