A Flexible Embedded SRAM IP Compiler

Static random access memory (SRAM) compiler is the silicon compiler that generates SRAM IP cores with various specifications. A high performance and flexible SRAM compiler is proposed in this paper. Our compiler uses block assembly techniques with uniform physical data syntax. This encapsulates the compiler from low level module information. Hence it is self-adaptive to the migration of technology nodes. Our experiment result shows that this compiler can generate a wide capacity range of SRAM with relatively high performance.

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