Testing Core-Based Systems: A Symbolic Methodology

Because they must rely on vendor-provided test patterns, designers of core-based systems are forced to use expensive scan-based test techniques. The authors' alternative solution exploits the expressiveness of binary decision diagrams to provide test generation for the system and testability estimation and improvement of its components.

[1]  Alberto L. Sangiovanni-Vincentelli,et al.  Irredundant sequential machines via optimal logic synthesis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Prab Varma,et al.  A unifying methodology for intellectual property and custom logic testing , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[3]  Enrico Macii,et al.  BDD-based testability estimation of VHDL designs , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[4]  Enrico Macii,et al.  Test generation for networks of interacting FSMs using symbolic techniques , 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

[5]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[6]  Vishwani D. Agrawal,et al.  Functional test generation for synchronous sequential circuits , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Nur A. Touba,et al.  Testing embedded cores using partial isolation rings , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[8]  Franco Fummi,et al.  Functional design for testability of control-dominated architectures , 1997, TODE.

[9]  Kwang-Ting Cheng On removing redundancy in sequential circuits , 1991, 28th ACM/IEEE Design Automation Conference.