Ultra-Shallow Junction Formation by Non-Melt Laser Spike Annealing and its Application to Complementary Metal Oxide Semiconductor Devices in 65-nm Node

We activated source/drain junctions of complementary metal oxide semiconductor (CMOS) by simply replacing rapid thermal annealing (RTA) in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers, unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better Vth roll-offs and larger drain currents compared to those formed by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.

[1]  Somit Talwar,et al.  Ultra-shallow, abrupt, and highly-activated junctions by low-energy ion implantation and laser annealing , 1998, 1998 International Conference on Ion Implantation Technology. Proceedings (Cat. No.98EX144).

[2]  T. Mogami,et al.  High performance 50-nm physical gate length pMOSFETs by using low temperature activation by re-crystallization scheme , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[3]  50 nm SOI CMOS transistors with ultra shallow junction using laser annealing and pre-amorphization implantation , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).