An approach to a design for testability personal consultant

Abstract The paper will propose a new approach to the problem of the design of testable structures: a hierarchical testability analyzer determines testability of the design at the different phases of its development, determining the regions of untestability and the causes. This information is then passed to a design for testability expert system which can work at the different levels of abstraction of the design representation. This knowledge based system analyzes the different areas and causes of untestability, then chooses, by searching into its knowledge base, the best design for testability technique that solves the testability problem and finally explains to the designer how the result has been derived. The solution satisfies a set of user-defined constraints on the final VLSI implementation such as area, pins, time delays requirements.