HIGH PERFORMANCE RNS FOR QR DECOMPOSITION MATRIX INVERSION ARCHITECTURE

Field Programmable Gate Arrays (FPGA) is emerged in many Digital Signal Processing (DSP) applications with the inclusion of dedicated core processing elements as logical blocks. But the technology remains limited in its ability to support high speed demands which gives rise to unified arithmetic models for performing some core functional units. This paper presents high performance RNS (Residue Number System) arithmetic for Q-R decomposition (QRD) to perform matrix inverse core which limits the overall system performance of FPGA implementation of OMP algorithm for compressive sensing signal reconstruction. In this article is also introduced a new memory efficient on-chip Ram-based) reverse conversion unit capable of performing high speed RNS computation. This hardware-optimized RNS architecture can take wide range of input operand sizes with different sets of moduli sets. The design is implemented in an ALTERA FPGA Cyclone-II device. Experimental results proved that this memory efficient reverse conversion RNS architecture outperforms all other state–of–the–art FPGA implementations.