Minimizing Energy Consumption for Embedded Multicore Systems Using Cache Configuration and Task Mapping

Caches are known for their effectiveness in alleviating the speed gap between processor and off-chip memory. But its energy consumption is a concern. In this paper, we proposed two approaches based on cache configuration(cache reconfiguration and cache partitioning) and task mapping that aim to optimize the energy consumption of caches on embedded multi-core systems. The first approach is optimal and based oninteger linear programming (ILP), whereas the second approach is a genetic algorithm (GA) that is near-optimal, but scalable with low overhead. Experimental results demonstrate that our ILP based approach can achieve 11.1% energy saving on average compared to previous techniques, GA based approach can reduce 9.7% energy consumption on average.

[1]  Lui Sha,et al.  Impact of Cache Partitioning on Multi-tasking Real Time Embedded Systems , 2008, 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications.

[2]  Gang Chen,et al.  Cache partitioning and scheduling for energy optimization of real-time MPSoCs , 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.

[3]  Sanjay Ranka,et al.  Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[4]  Stefan M. Petters,et al.  Enhanced Race-To-Halt: A Leakage-Aware Energy Management Approach for Dynamic Priority Systems , 2011, 2011 23rd Euromicro Conference on Real-Time Systems.

[5]  Kamran Rahmani,et al.  Synergistic integration of dynamic cache reconfiguration and code compression in embedded systems , 2011, 2011 International Green Computing Conference and Workshops.

[6]  Mehdi Modarressi,et al.  A Reconfigurable Cache Architecture for Object-Oriented Embedded Systems , 2006, 2006 Canadian Conference on Electrical and Computer Engineering.

[7]  Paul Lokuciejewski,et al.  WCET-aware Software Based Cache Partitioning for Multi-Task Real-Time Systems , 2009, WCET.

[8]  Minming Li,et al.  Task Assignment with Cache Partitioning and Locking for WCET Minimization on MPSoC , 2010, 2010 39th International Conference on Parallel Processing.

[9]  Kaushik Roy,et al.  An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[10]  Margo Seltzer,et al.  Cache-Fair Thread Scheduling for Multicore Processors , 2006 .

[11]  Frank Vahid,et al.  A highly configurable cache for low energy embedded systems , 2005, TECS.

[12]  James H. Anderson,et al.  Cache-Aware Real-Time Scheduling on Multicore Platforms: Heuristics and a Case Study , 2008, 2008 Euromicro Conference on Real-Time Systems.

[13]  Francky Catthoor,et al.  Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems , 2012, Journal of Signal Processing Systems.

[14]  Gerard J. M. Smit,et al.  A mathematical approach towards hardware design , 2010, Dynamically Reconfigurable Architectures.

[15]  Peter Petrov,et al.  Cache partitioning for energy-efficient and interference-free embedded multitasking , 2010, TECS.

[16]  Jan Gustafsson,et al.  The Mälardalen WCET Benchmarks: Past, Present And Future , 2010, WCET.

[17]  Wayne H. Wolf,et al.  A task-level hierarchical memory model for system synthesis of multiprocessors , 1997, DAC.