System-Level Design

[1]  Alice C. Parker,et al.  SOS: Synthesis of application-specific heterogeneous multiprocessor systems , 2001, J. Parallel Distributed Comput..

[2]  Axel Jantsch,et al.  The Rugby Model: a conceptual frame for the study of modelling, analysis and synthesis concepts of electronic systems , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[3]  C. P. Ravikumar,et al.  FREEDOM: statistical behavioral estimation of system energy and power , 1998, Proceedings Eleventh International Conference on VLSI Design.

[4]  Anthony A. Maciejewski,et al.  Task Matching and Scheduling in Heterogenous Computing Environments Using a Genetic-Algorithm-Based Approach , 1997, J. Parallel Distributed Comput..

[5]  Yervant Zorian,et al.  Introducing Core-Based System Design , 1997, IEEE Des. Test Comput..

[6]  Yanbing Li,et al.  A Task-level Hierarchical Memory Model For System Synthesis Of Multiprocessors , 1997, Proceedings of the 34th Design Automation Conference.

[7]  A. Parker,et al.  Incorporating Imprecise Computation Into System-level Design Of Application-specific Heterogeneous Multiprocessors , 1997, Proceedings of the 34th Design Automation Conference.

[8]  C. P. Ravikumar,et al.  Rapid synthesis of multi-chip systems , 1997, Proceedings Tenth International Conference on VLSI Design.

[9]  Daniel Brand,et al.  Inaccuracies in power estimation during logic synthesis , 1996, Proceedings of International Conference on Computer Aided Design.

[10]  Kishan G. Mehrotra,et al.  A study of approximating the moments of the job completion time in PERT networks , 1996 .

[11]  Jan M. Rabaey,et al.  Activity-sensitive architectural power analysis , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Wonyong Sung,et al.  Simulation-based word-length optimization method for fixed-point digital signal processing systems , 1995, IEEE Trans. Signal Process..

[13]  Wayne H. Wolf,et al.  Performance estimation for real-time distributed embedded systems , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[14]  J. R. Armstrong,et al.  Generating Simulation Models from Natural Language Specifications , 1995, Simul..

[15]  Tet Hin Yeap,et al.  VLSI implementation of discrete wavelet transform , 1995, Proceedings of Eighth International Application Specific Integrated Circuits Conference.

[16]  Yu Hen Hu,et al.  Multiprocessor implementation of real-time DSP algorithms , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[17]  Alice C. Parker,et al.  A methodology and design tools to support system-level VLSI design , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[18]  Vinod K. Agarwal,et al.  A Specification-Driven Architectural Design Environment , 1995, Computer.

[19]  Frank Vahid,et al.  SpecCharts: a VHDL front-end for embedded systems , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Edward A. Lee,et al.  Managing complexity in heterogeneous system specification, simulation, and synthesis , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

[21]  Krithi Ramamritham,et al.  Allocation and Scheduling of Precedence-Related Periodic Tasks , 1995, IEEE Trans. Parallel Distributed Syst..

[22]  C. P. Ravikumar,et al.  Genetic algorithm for mapping tasks onto a reconfigurable parallel processor , 1995 .

[23]  Mani B. Srivastava,et al.  System level hardware module generation , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[24]  Alice C. Parker,et al.  Optimal synthesis of application specific heterogeneous pipelined multiprocessors , 1994, Proceedings of IEEE International Conference on Application Specific Array Processors (ASSAP'94).

[25]  Bill Lin,et al.  A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules , 1994, 31st Design Automation Conference.

[26]  Alice C. Parker,et al.  Experience with Image Compression Chip Design Using Unified System Construction Tools , 1994, 31st Design Automation Conference.

[27]  Dake Liu,et al.  Power consumption estimation in CMOS VLSI chips , 1994, IEEE J. Solid State Circuits.

[28]  Joseph Y.-T. Leung,et al.  Minimizing Maximum Weighted Error for Imprecise Computation Tasks , 1994, J. Algorithms.

[29]  Frank Vahid,et al.  A system-design methodology: executable-specification refinement , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[30]  Nirwan Ansari,et al.  A Genetic Algorithm for Multiprocessor Scheduling , 1994, IEEE Trans. Parallel Distributed Syst..

[31]  Thomas P. Barnwell,et al.  Optimal automatic periodic multiprocessor scheduler for fully specified flow graphs , 1993, IEEE Trans. Signal Process..

[32]  Uwe Schwiegelshohn,et al.  Allocating communication channels to parallel tasks , 1993 .

[33]  Frank Vahid,et al.  Specification partitioning for system design , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[34]  Alice C. Parker,et al.  Synthesis of Application-Specific Heterogeneous Multiprocessor Systems , 1992, [1992] Proceedings the 19th Annual International Symposium on Computer Architecture.

[35]  Frank Vahid,et al.  A survey of behavioral-level partitioning systems , 1991 .

[36]  Donald E. Thomas,et al.  Architectural partitioning for system level synthesis of integrated circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[37]  Bing Zeng,et al.  Analysis of floating point roundoff errors using dummy multiplier coefficient sensitivities , 1991 .

[38]  Alice C. Parker,et al.  CHOP: a constraint-driven system-level partitioner , 1991, 28th ACM/IEEE Design Automation Conference.

[39]  Wei-Kuan Shih,et al.  Algorithms for scheduling imprecise computations , 1991, Computer.

[40]  Mayez A. Al-Mouhamed,et al.  Lower Bound on the Number of Processors and Time for Scheduling Precedence Graphs with Communication Costs , 1990, IEEE Trans. Software Eng..

[41]  Edward A. Lee,et al.  Architectures for Statically Scheduled Dataflow , 1990, J. Parallel Distributed Comput..

[42]  Jane N. Hagstrom,et al.  Computing the probability distribution of project duration in a PERT network , 1990, Networks.

[43]  Kang G. Shin,et al.  Static allocation of periodic tasks with precedence constraints in distributed real-time systems , 1989, [1989] Proceedings. The 9th International Conference on Distributed Computing Systems.

[44]  J. Stankovic,et al.  Efficient Scheduling Algorithms for Real-Time Multiprocessor Systems , 1989, IEEE Trans. Parallel Distributed Syst..

[45]  Emile K. Haddad,et al.  Optimal Load Allocation for Parallel and Distributed Processing , 1989 .

[46]  Frank D. Anger,et al.  Scheduling Precedence Graphs in Systems with Interprocessor Communication Times , 1989, SIAM J. Comput..

[47]  David M. Nicol,et al.  Optimal Partitioning of Random Programs Across two Processors , 1989, IEEE Trans. Software Eng..

[48]  Joos Vandewalle,et al.  Simulated‐annealing‐based optimization of coefficient and data word‐lengths in digital filters , 1988 .

[49]  Jing-Jang Hwang,et al.  Multiprocessor scheduling with interprocessor communication delays , 1988 .

[50]  H. V. Jagadish,et al.  Partitioning techniques for large-grained parallelism , 1988, Seventh Annual International Phoenix Conference on Computers an Communications. 1988 Conference Proceedings.

[51]  Alice C. Parker,et al.  PHRAN-SPAN: A Natural Language Interface for System Specifications , 1987, 24th ACM/IEEE Design Automation Conference.

[52]  Shahid H. Bokhari,et al.  Assignment Problems in Parallel and Distributed Computing , 1987 .

[53]  David Harel,et al.  Statecharts: A Visual Formalism for Complex Systems , 1987, Sci. Comput. Program..

[54]  S. Purushothaman Iyer,et al.  Reasoning About Probabilistic Behavior in Concurrent Systems , 1987, IEEE Transactions on Software Engineering.

[55]  Alexander Thomasian,et al.  Analytic Queueing Network Models for Parallel Processing of Task Systems , 1986, IEEE Transactions on Computers.

[56]  Vidyadhar G. Kulkarni,et al.  Markov and Markov-Regenerative pert Networks , 1986, Oper. Res..

[57]  Bipin Indurkhya,et al.  Optimal partitioning of randomly generated distributed programs , 1986, IEEE Transactions on Software Engineering.

[58]  Jerzy Kamburowski,et al.  An upper bound on the expected completion time of PERT networks , 1985 .

[59]  W.P. Birmingham,et al.  MICON: A Knowledge Based Single Board Computer Designer , 1984, 21st Design Automation Conference Proceedings.

[60]  Alice C. Parker,et al.  Automated Synthesis of Digital Hardware , 1982, IEEE Transactions on Computers.

[61]  Markku Renfors,et al.  The maximum sampling rate of digital filters under hardware speed constraints , 1981 .

[62]  Wesley W. Chu,et al.  Task Allocation in Distributed Data Processing , 1980, Computer.

[63]  Jeffrey M. Jaffe,et al.  Bounds on the Scheduling of Typed Task Systems , 1980, SIAM J. Comput..

[64]  Shahid H. Bokhari,et al.  Control of Distributed Processes , 1978, Computer.

[65]  Pierre N. Robillard,et al.  The Completion Time of PERT Networks , 1977, Oper. Res..

[66]  Ronald L. Graham,et al.  Bounds for Multiprocessor Scheduling with Resource Constraints , 1975, SIAM J. Comput..

[67]  Eduardo B. Fernández,et al.  Bounds on the Number of Processors and Time for Multiprocessor Optimal Schedules , 1973, IEEE Transactions on Computers.

[68]  A. Newell,et al.  Computer Structures: Readings and Examples, , 1971 .

[69]  Salah E. Elmaghraby,et al.  The Theory of Networks and Management Science: Part II , 1970 .

[70]  Józef Łukaszewicz,et al.  Letter to the Editor-On the Estimation of Errors Introduced by Standard Assumptions Concerning the Distribution of Activity Duration in PERT Calculations , 1965 .

[71]  D. R. Fulkerson.  Expected Critical Path Lengths in PERT Networks , 1962 .

[72]  D. Malcolm,et al.  Application of a Technique for Research and Development Program Evaluation , 1959 .

[73]  Alice C. Parker,et al.  A comprehensive framework for the specification of hardware/software systems , 2001 .

[74]  Alice C. Parker,et al.  Accuracy sensitive word-length selection for algorithm optimization , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[75]  Jianwen Zhu,et al.  Specification and Design of Embedded Systems , 1998, Informationstechnik Tech. Inform..

[76]  Alice C. Parker,et al.  Theory and practice in system-level design of application-specific heterogeneous multiprocessors , 1997 .

[77]  Zbigniew Michalewicz,et al.  Genetic Algorithms + Data Structures = Evolution Programs , 1996, Springer Berlin Heidelberg.

[78]  Edwin Hsing-Mean Sha,et al.  Optimizing DSP flow graphs via schedule-based multidimensional retiming , 1996, IEEE Trans. Signal Process..

[79]  Wfj Wim Verhaegh,et al.  Multidimensional periodic scheduling , 1995 .

[80]  Miodrag Potkonjak,et al.  Optimal ILP-based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming , 1995, 32nd Design Automation Conference.

[81]  Imtiaz Ahmad,et al.  Synthesis of application-specific multiprocessor systems , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[82]  Alice C. Parker,et al.  Unified System Construction (USC) , 1991 .

[83]  Fadi J. Kurdahi,et al.  Techniques for area estimation of VLSI layouts , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[84]  W.P. Birmingham,et al.  MICON: a single-board computer synthesis tool , 1988, IEEE Circuits and Devices Magazine.

[85]  Alice C. Parker,et al.  Stochastic Models for Wireability Analysis of Gate Arrays , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[86]  Sarosh Talukdar,et al.  Scheduling of tasks for distributed processors , 1984, ISCA '84.