Characterization and Model Parameter Extraction of Symmetrical Centre Tapped Inductor using Build in Mixed Mode and Pure Differential S-Parameters

With the continuous reduction of the gate length, the cut off frequency of the active devices in CMOS technology has exceeded 200 GHz [1]. In addition, CMOS possesses the capability to integrate transceiver with the baseband circuits. Thus, CMOS technology seems to be an attractive candidate for low-gigahertz (5 GHz) radio frequency (RF) applications [2] and even millimetre wave one [3]. Then, monolithic inductors have become an important component in highly integrated radio frequency circuits (RF ICs) for wireless communication systems such as personal communication services, wireless local area networks, satellite communications, and the global positioning system. It is well known that exciting a spiral inductor differentially, using a source connected between the two ends of the inductor, the peak Q-factor shows a significant increase, and this high Q value is maintained over a broader bandwidth [4] compared to single-ended excitation. Up to now, differential characterization of symmetrical inductor has been performed using classical single ended S-parameters [5], and assuming linearity and electrical symmetry hypothesis, mixed mode Sparameters are then computed and differential quality factor extracted. In this paper, for the first time using recently available vector network analyzer capable of delivering true differential signal, PNA-X from Agilent, we will verify this hypothesis discussing dedicated differential test structure and methodology. Moreover, from the modelling side new perspective will be proposed in order to take advantage of mixed mode S-parameters to extract new parameter such as self mutual inductance.

[1]  R. J. Havens,et al.  Impact of probe configuration and calibration techniques on quality factor determination of on-wafer inductors for GHz applications , 2002, Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002..

[2]  W.R. Eisenstadr,et al.  Common and differential crosstalk characterization on the silicon substrate , 1999, IEEE Microwave and Guided Wave Letters.

[3]  M. Hargrove,et al.  RF potential of a 0.18-/spl mu/m CMOS logic device technology , 2000 .

[4]  M. Hargrove,et al.  RF Potential of a 0 . 18-m CMOS Logic Device Technology , 2000 .

[5]  J.A.M. Geelen,et al.  An improved de-embedding technique for on-wafer high-frequency characterization , 1991, Proceedings of the 1991 Bipolar Circuits and Technology Meeting.

[6]  R.W. Brodersen,et al.  60 GHz CMOS radio for Gb/s wireless LAN , 2004, 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers.

[7]  J. Long,et al.  A Q-factor enhancement technique for MMIC inductors , 1998, 1998 IEEE MTT-S International Microwave Symposium Digest (Cat. No.98CH36192).

[8]  D. Gloria,et al.  High frequency low noise potentialities of down to 65 nm technology nodes MOSFETs , 2005, European Gallium Arsenide and Other Semiconductor Application Symposium, GAAS 2005.