The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor

As MOSFET is scaled below 90 nm, many daunting challenges arise. Short-channel effects (SCEs; drain-induced barrier lowering and VTHmiddotrolloff), off-state leakage, parasitic capacitance, and resistance severely limit the performance of these transistors. New device innovations are essential to overcome these difficulties. In this paper, we propose the concept of a novel tunnel source (PNPN) n-MOSFET based on the principle of band-to- band tunneling. It is found that the PNPN n-MOSFET has the potential of steep subthreshold swing and improved Ion in addition to immunities against SCEs. Therefore, such a PNPN n-MOSFET can overcome the ever-degrading on-off characteristics of the deeply scaled conventional MOSFET. The design of the PNPN n-MOSFET was extensively examined using simulations. Devices with source-side tunneling junctions were fabricated on bulk substrates using spike anneal, and the experimental data is presented.

[1]  G. Amaratunga,et al.  Silicon surface tunnel transistor , 1995 .

[2]  H. Kisaki,et al.  Tunnel transistor , 1973 .

[3]  K.P. MacWilliams,et al.  Enhancement-mode quantum-well Ge/sub x/Si/sub 1-x /PMOS , 1991, IEEE Electron Device Letters.

[4]  L. Esaki Long Journey into Tunneling , 1974, Science.

[5]  Digh Hisamoto,et al.  A 0.1 mu m-gate elevated source and drain MOSFET fabricated by phase-shifted lithography , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[6]  T. Tezuka,et al.  High velocity electron injection MOSFETs for ballistic transistors using SiGe/strained-Si heterojunction source structures , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[7]  Jason C. S. Woo,et al.  ASYMMETRIC TUNNELING SOURCE MOSFETS: A NOVEL DEVICE SOLUTION FOR SUB-100NM CMOS TECHNOLOGY , 2006 .

[8]  D. Klaassen,et al.  A new recombination model for device simulation including tunneling , 1992 .

[9]  G. Bersuker,et al.  Conventional n-channel MOSFET devices using single layer HfO/sub 2/ and ZrO/sub 2/ as high-k gate dielectrics with polysilicon gate electrode , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[10]  Qin Zhang,et al.  Low-subthreshold-swing tunnel transistors , 2006, IEEE Electron Device Letters.

[11]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[12]  Sorin Cristoloveanu,et al.  Ultrathin silicon-on-insulator vertical tunneling transistor , 2003 .

[13]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[14]  S. Luryi,et al.  Lateral interband tunneling transistor in silicon-on-insulator , 2004 .

[15]  I. Eisele,et al.  Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering , 2005, IEEE Transactions on Electron Devices.

[16]  Vivek Subramanian,et al.  Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel , 2002 .

[17]  D. Frank,et al.  Universal tunneling behavior in technologically relevant P/N junction diodes , 2004 .

[18]  S. Sedlmaier,et al.  Vertical tunnel field-effect transistor , 2004, IEEE Transactions on Electron Devices.

[19]  K. Gopalakrishnan,et al.  Impact ionization MOS (I-MOS)-Part II: experimental results , 2005, IEEE Transactions on Electron Devices.

[20]  E. Kane Zener tunneling in semiconductors , 1960 .

[21]  Paul R. Berger,et al.  Current-voltage characteristics of high current density silicon Esaki diodes grown by molecular beam epitaxy and the influence of thermal annealing , 2000 .

[22]  P.B. Griffin,et al.  Impact ionization MOS (I-MOS)-Part I: device and circuit simulations , 2005, IEEE Transactions on Electron Devices.