Architecture Design of an Area Efficient High Speed Crypto Processor for 4G LTE
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[1] Anupam Chattopadhyay,et al. Designing integrated accelerator for stream ciphers with structural similarities , 2012, Cryptography and Communications.
[2] O. Koufopavlou,et al. Area optimized architecture and VLSI implementation of a multi-coder processor for the WTLS , 2003, 2003 46th Midwest Symposium on Circuits and Systems.
[3] Sunggu Lee,et al. Design and implementation of a private and public key crypto processor and its application to a security system , 2004, IEEE Trans. Consumer Electron..
[4] Paris Kitsos,et al. UMTS security: system architecture and hardware implementation: Research Articles , 2007 .
[5] Sebastian Hessel,et al. Implementation and Benchmarking of Hardware Accelerators for Ciphering in LTE Terminals , 2009, GLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference.
[6] Giorgio Di Natale,et al. Challenges in designing trustworthy cryptographic co-processors , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).
[7] Nicolas Sklavos,et al. LTE/SAE Security Issues on 4G Wireless Networks , 2013, IEEE Security & Privacy.
[8] Nicolas Sklavos. On the Hardware Implementation Cost of Crypto-Processors Architectures , 2010, Inf. Secur. J. A Glob. Perspect..
[9] Kouichi Itoh,et al. A Very Compact Hardware Implementation of the KASUMI Block Cipher , 2010, WISTP.
[10] Athanassios N. Skodras,et al. FPGA-based performance analysis of stream ciphers ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0 , 2013, Microprocess. Microsystems.
[11] Sebastian Hessel,et al. An optimized parallel and energy-efficient implementation of SNOW 3G for LTE mobile devices , 2010, 2010 IEEE 12th International Conference on Communication Technology.