A 4×9 Gb/s 1pJ/b Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects
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[1] Ramesh Harjani,et al. A 6-Gb/s MIMO Crosstalk Cancellation Scheme for High-Speed I/Os , 2011, IEEE Journal of Solid-State Circuits.
[2] Yusuf Leblebici,et al. Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces , 2015, IEEE Journal of Solid-State Circuits.
[3] Shreyas Sen,et al. A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.
[4] Jae-Yoon Sim,et al. A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control , 2009, IEEE Journal of Solid-State Circuits.
[5] Azita Emami-Neyestanak,et al. A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation , 2011, IEEE Journal of Solid-State Circuits.
[6] James E. Jaussi,et al. A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS , 2008, IEEE Journal of Solid-State Circuits.
[7] Jason Cong,et al. Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System , 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.
[8] Thomas Toifl,et al. A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[9] Patrick Reynaert,et al. 10.2 An FSK plastic waveguide communication link in 40nm CMOS , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.
[10] Jongsun Kim,et al. An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling , 2012, IEEE Journal of Solid-State Circuits.
[11] Young-Hyun Jun,et al. A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme , 2008, 2008 IEEE Custom Integrated Circuits Conference.
[12] Christian Menolfi,et al. A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS , 2012, IEEE Journal of Solid-State Circuits.
[13] Behzad Razavi. Design of intergrated circuits for optical communications , 2002 .
[14] Volkan Cevher,et al. A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).
[15] Yusuf Leblebici,et al. A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).
[16] W.T. Beyene,et al. Controlled Intersymbol Interference Design Techniques of Conventional Interconnect Systems for Data Rates Beyond 20 Gbps , 2008, IEEE Transactions on Advanced Packaging.
[17] Thomas Toifl,et al. A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology , 2012, 2012 IEEE International Solid-State Circuits Conference.
[18] Amir Amirkhany,et al. A Low-Cost Resonance Mitigation Technique for Multidrop Memory Interfaces , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.
[19] Yusuf Leblebici,et al. 10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.
[20] V. Stojanovic,et al. A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter , 2008, IEEE Journal of Solid-State Circuits.
[21] Ramesh Harjani,et al. A 12-Gb/s Multichannel I/O Using MIMO Crosstalk Cancellation and Signal Reutilization in 65-nm CMOS , 2013, IEEE Journal of Solid-State Circuits.