High voltage GaN based transistors already showed promising de-vice properties which makes them very attractive for future highly efficient power switching application. To further optimize device switching performance at high bias voltages the dependency of de-vice breakdown and dynamic effects on device layer epitaxy and processing has to be analyzed. This paper discusses the dependen-cies of breakdown events, predominantly vertical breakdown be-tween the device on the chip front side and the conductive n-type SiC or Si substrate on various technological parameters. They comprise high voltage buffer design and material quality, SiC sub-strate conductivity as well as metal contact technology of GaN HEMT devices. Furthermore a correlation between many of those parameters and dynamic switching properties has been determined. Physical mechanisms are then proposed to explain the basic inter-dependencies.