论文信息 - Dynamic RAM for on-chip instruction caches

Dynamic RAM for on-chip instruction caches

On-chip memories are commonly used to reduce the external communication bandwidth of current microprocessors. Implementations with static RAM allow simple synchronization structures. The use of dynamic RAM results in an important area saving but complicates the processor control due to the refresh requirements. In this paper, a simple design approach, based on the use of dynamic RAM, is introduced for implementing on-chip instruction caches without complicating the processor control.

Jordi Cortadella | Teodor Jové | J. Cortadella | T. Jové

[1] Emmanuel Katevenis,et al. Reduced instruction set computer architectures for VLSI , 1984 .

[2] Emmanuel Katevenis. Reduced instruction set computer architectures for vlsi (microprocessor, risc, multiple-windows - of - registers) , 1983 .

[3] T. Sridhar,et al. A 553K-transistor LISP processor chip , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4] Veljko M. Milutinovic,et al. An Introduction to GaAs Microprocessor Architecture for VLSI , 1986, Computer.

[5] Anant Agarwal,et al. On-Chip Instruction Caches for High Performance Processors, , 1987 .

[6] Theodore W. Houston,et al. A 553 K-transistor LISP processor chip , 1987 .